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wr2rf-vme
Commit ec477a91 authored by John Gill's avatar John Gill
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Merge branch 'oddr'

parents cc62b02b 2b36b08b
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Showing with 386 additions and 413 deletions
hdl/rtl/Manifest.py
View file @ ec477a91
......@@ -13,6 +13,7 @@ files = ['vtu_blk.vhd',
'wr2rf_ocxo.vhd',
'wr2rf_lemo.vhd',
'wr2rf_dds.vhd',
'x8oddr.vhd',
'ila_syn.vhd'];
hdl/rtl/registers/trigunit_regs.cheby
View file @ ec477a91
......@@ -236,21 +236,6 @@ memory-map:
access: ro
x-fesa:
persistence: PPM
- reg:
name: syncIDelay
description: Delay on the sync input
width: 16
access: rw
x-hdl:
write-strobe: True
children:
- field:
name: delay
description: value
range: 4-0
preset: 0x0
x-hdl:
type: wire
- reg:
name: trigOHCDelay
description: Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay
......@@ -266,21 +251,12 @@ memory-map:
description: Delay on the trigger output
width: 16
access: rw
x-hdl:
write-strobe: True
children:
- field:
name: delay
description: value
range: 4-0
preset: 0x0
x-hdl:
type: wire
- reg:
name: trigOutProgDelay
description: Delay the trigger output by a fraction of the RF clock, 1/8ths - hot-1 encoded
width: 16
access: rw
- submap:
name: trigdiag
filename: vtudiag_regs.cheby
......
hdl/rtl/registers/trigunit_regs.vhd
View file @ ec477a91
-- Do not edit. Generated on Mon Mar 15 17:22:42 2021 by jgill
-- Do not edit. Generated on Wed Mar 24 16:37:30 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......@@ -73,23 +73,12 @@ entity trigunit_regs is
-- Used in windowedOperation mode
wValueOnline_i : in std_logic_vector(63 downto 0);
-- Delay on the sync input
-- value
syncIDelay_delay_i : in std_logic_vector(4 downto 0);
syncIDelay_delay_o : out std_logic_vector(4 downto 0);
syncIDelay_wr_o : out std_logic;
-- Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay
trigOHCDelay_set_o : out std_logic;
-- Delay on the trigger output
-- value
trigODelay_delay_i : in std_logic_vector(4 downto 0);
trigODelay_delay_o : out std_logic_vector(4 downto 0);
trigODelay_wr_o : out std_logic;
-- Delay the trigger output by a fraction of the RF clock, 1/8ths - hot-1 encoded
trigOutProgDelay_o : out std_logic_vector(15 downto 0);
-- Control register
-- Enable the unit
......@@ -136,14 +125,12 @@ architecture syn of trigunit_regs is
signal wValueOffline_reg : std_logic_vector(63 downto 0);
signal wValueOffline_wreq : std_logic_vector(3 downto 0);
signal wValueOffline_wack : std_logic_vector(3 downto 0);
signal syncIDelay_wreq : std_logic;
signal trigOHCDelay_set_reg : std_logic;
signal trigOHCDelay_wreq : std_logic;
signal trigOHCDelay_wack : std_logic;
signal trigODelay_delay_reg : std_logic_vector(4 downto 0);
signal trigODelay_wreq : std_logic;
signal trigOutProgDelay_reg : std_logic_vector(15 downto 0);
signal trigOutProgDelay_wreq : std_logic;
signal trigOutProgDelay_wack : std_logic;
signal trigODelay_wack : std_logic;
signal trigdiag_control_enable_reg : std_logic;
signal trigdiag_control_window_reg : std_logic_vector(2 downto 0);
signal trigdiag_control_wreq : std_logic;
......@@ -336,10 +323,6 @@ begin
-- Register wValueOnline
-- Register syncIDelay
syncIDelay_delay_o <= wr_dat_d0(4 downto 0);
syncIDelay_wr_o <= syncIDelay_wreq;
-- Register trigOHCDelay
trigOHCDelay_set_o <= trigOHCDelay_set_reg;
process (clk_i) begin
......@@ -357,21 +340,17 @@ begin
end process;
-- Register trigODelay
trigODelay_delay_o <= wr_dat_d0(4 downto 0);
trigODelay_wr_o <= trigODelay_wreq;
-- Register trigOutProgDelay
trigOutProgDelay_o <= trigOutProgDelay_reg;
trigODelay_delay_o <= trigODelay_delay_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trigOutProgDelay_reg <= "0000000000000000";
trigOutProgDelay_wack <= '0';
trigODelay_delay_reg <= "00000";
trigODelay_wack <= '0';
else
if trigOutProgDelay_wreq = '1' then
trigOutProgDelay_reg <= wr_dat_d0;
if trigODelay_wreq = '1' then
trigODelay_delay_reg <= wr_dat_d0(4 downto 0);
end if;
trigOutProgDelay_wack <= trigOutProgDelay_wreq;
trigODelay_wack <= trigODelay_wreq;
end if;
end if;
end process;
......@@ -402,16 +381,14 @@ begin
-- Register trigdiag_counter
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, control_wack, configOffline_wack, bValueOffline_wack, htValueOffline_wack, wValueOffline_wack, trigOHCDelay_wack, trigOutProgDelay_wack, trigdiag_control_wack) begin
process (wr_adr_d0, wr_req_d0, control_wack, configOffline_wack, bValueOffline_wack, htValueOffline_wack, wValueOffline_wack, trigOHCDelay_wack, trigODelay_wack, trigdiag_control_wack) begin
control_wreq <= '0';
configOffline_wreq <= '0';
bValueOffline_wreq <= (others => '0');
htValueOffline_wreq <= (others => '0');
wValueOffline_wreq <= (others => '0');
syncIDelay_wreq <= '0';
trigOHCDelay_wreq <= '0';
trigODelay_wreq <= '0';
trigOutProgDelay_wreq <= '0';
trigdiag_control_wreq <= '0';
case wr_adr_d0(6 downto 3) is
when "0000" =>
......@@ -555,21 +532,13 @@ begin
when "1000" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg syncIDelay
syncIDelay_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg trigOHCDelay
trigOHCDelay_wreq <= wr_req_d0;
wr_ack_int <= trigOHCDelay_wack;
when "10" =>
when "01" =>
-- Reg trigODelay
trigODelay_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg trigOutProgDelay
trigOutProgDelay_wreq <= wr_req_d0;
wr_ack_int <= trigOutProgDelay_wack;
wr_ack_int <= trigODelay_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
......@@ -618,7 +587,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, status_wrongWvalue_i, status_wrongHTvalue_i, status_wrongBvalue_i, status_running_i, status_startReady_i, status_missReady_i, status_missValid_i, control_vtuReset_reg, configOffline_valid_i, configOffline_htSwitchingEnable_reg, configOffline_mode_reg, bValueOffline_reg, htValueOffline_reg, wValueOffline_reg, configOnline_htSwitchingEnable_i, configOnline_mode_i, bValueOnline_i, htValueOnline_i, wValueOnline_i, syncIDelay_delay_i, trigOHCDelay_set_reg, trigODelay_delay_i, trigOutProgDelay_reg, trigdiag_control_window_reg, trigdiag_control_enable_reg, trigdiag_generation_i, trigdiag_freq_i, trigdiag_counter_i) begin
process (adr_int, rd_req_int, status_wrongWvalue_i, status_wrongHTvalue_i, status_wrongBvalue_i, status_running_i, status_startReady_i, status_missReady_i, status_missValid_i, control_vtuReset_reg, configOffline_valid_i, configOffline_htSwitchingEnable_reg, configOffline_mode_reg, bValueOffline_reg, htValueOffline_reg, wValueOffline_reg, configOnline_htSwitchingEnable_i, configOnline_mode_i, bValueOnline_i, htValueOnline_i, wValueOnline_i, trigOHCDelay_set_reg, trigODelay_delay_reg, trigdiag_control_window_reg, trigdiag_control_enable_reg, trigdiag_generation_i, trigdiag_freq_i, trigdiag_counter_i) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(6 downto 3) is
......@@ -796,24 +765,15 @@ begin
when "1000" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg syncIDelay
rd_ack_d0 <= rd_req_int;
rd_dat_d0(4 downto 0) <= syncIDelay_delay_i;
rd_dat_d0(15 downto 5) <= (others => '0');
when "01" =>
-- Reg trigOHCDelay
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= trigOHCDelay_set_reg;
rd_dat_d0(15 downto 1) <= (others => '0');
when "10" =>
when "01" =>
-- Reg trigODelay
rd_ack_d0 <= rd_req_int;
rd_dat_d0(4 downto 0) <= trigODelay_delay_i;
rd_dat_d0(4 downto 0) <= trigODelay_delay_reg;
rd_dat_d0(15 downto 5) <= (others => '0');
when "11" =>
-- Reg trigOutProgDelay
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= trigOutProgDelay_reg;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
......
hdl/rtl/registers/wr2rf_init_rf_ch_regs.cheby
View file @ ec477a91
......@@ -39,6 +39,10 @@ memory-map:
name: fdelay
range: 10-7
preset: 0
- field:
name: odelay
range: 15-11
preset: 0
- repeat:
name: ch
count: 2
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ ec477a91
-- Do not edit. Generated on Mon Mar 15 17:22:43 2021 by jgill
-- Do not edit. Generated on Wed Mar 24 16:37:31 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......@@ -28,6 +28,7 @@ entity wr2rf_init_rf_regs is
-- Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit.
rf1_t1_sync_progdelay_cdelay_o : out std_logic_vector(6 downto 0);
rf1_t1_sync_progdelay_fdelay_o : out std_logic_vector(3 downto 0);
rf1_t1_sync_progdelay_odelay_o : out std_logic_vector(4 downto 0);
-- REG csr
rf1_ch_0_csr_delay_oen_o : out std_logic;
......@@ -55,6 +56,7 @@ entity wr2rf_init_rf_regs is
-- Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit.
rf2_t1_sync_progdelay_cdelay_o : out std_logic_vector(6 downto 0);
rf2_t1_sync_progdelay_fdelay_o : out std_logic_vector(3 downto 0);
rf2_t1_sync_progdelay_odelay_o : out std_logic_vector(4 downto 0);
-- REG csr
rf2_ch_0_csr_delay_oen_o : out std_logic;
......@@ -95,6 +97,7 @@ architecture syn of wr2rf_init_rf_regs is
signal rf1_common_wack : std_logic;
signal rf1_t1_sync_progdelay_cdelay_reg : std_logic_vector(6 downto 0);
signal rf1_t1_sync_progdelay_fdelay_reg : std_logic_vector(3 downto 0);
signal rf1_t1_sync_progdelay_odelay_reg : std_logic_vector(4 downto 0);
signal rf1_t1_sync_progdelay_wreq : std_logic;
signal rf1_t1_sync_progdelay_wack : std_logic;
signal rf1_ch_0_csr_delay_oen_reg : std_logic;
......@@ -117,6 +120,7 @@ architecture syn of wr2rf_init_rf_regs is
signal rf2_common_wack : std_logic;
signal rf2_t1_sync_progdelay_cdelay_reg : std_logic_vector(6 downto 0);
signal rf2_t1_sync_progdelay_fdelay_reg : std_logic_vector(3 downto 0);
signal rf2_t1_sync_progdelay_odelay_reg : std_logic_vector(4 downto 0);
signal rf2_t1_sync_progdelay_wreq : std_logic;
signal rf2_t1_sync_progdelay_wack : std_logic;
signal rf2_ch_0_csr_delay_oen_reg : std_logic;
......@@ -232,16 +236,19 @@ begin
-- Register rf1_t1_sync_progdelay
rf1_t1_sync_progdelay_cdelay_o <= rf1_t1_sync_progdelay_cdelay_reg;
rf1_t1_sync_progdelay_fdelay_o <= rf1_t1_sync_progdelay_fdelay_reg;
rf1_t1_sync_progdelay_odelay_o <= rf1_t1_sync_progdelay_odelay_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rf1_t1_sync_progdelay_cdelay_reg <= "1001011";
rf1_t1_sync_progdelay_fdelay_reg <= "0000";
rf1_t1_sync_progdelay_odelay_reg <= "00000";
rf1_t1_sync_progdelay_wack <= '0';
else
if rf1_t1_sync_progdelay_wreq = '1' then
rf1_t1_sync_progdelay_cdelay_reg <= wr_dat_d0(6 downto 0);
rf1_t1_sync_progdelay_fdelay_reg <= wr_dat_d0(10 downto 7);
rf1_t1_sync_progdelay_odelay_reg <= wr_dat_d0(15 downto 11);
end if;
rf1_t1_sync_progdelay_wack <= rf1_t1_sync_progdelay_wreq;
end if;
......@@ -326,16 +333,19 @@ begin
-- Register rf2_t1_sync_progdelay
rf2_t1_sync_progdelay_cdelay_o <= rf2_t1_sync_progdelay_cdelay_reg;
rf2_t1_sync_progdelay_fdelay_o <= rf2_t1_sync_progdelay_fdelay_reg;
rf2_t1_sync_progdelay_odelay_o <= rf2_t1_sync_progdelay_odelay_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rf2_t1_sync_progdelay_cdelay_reg <= "1001011";
rf2_t1_sync_progdelay_fdelay_reg <= "0000";
rf2_t1_sync_progdelay_odelay_reg <= "00000";
rf2_t1_sync_progdelay_wack <= '0';
else
if rf2_t1_sync_progdelay_wreq = '1' then
rf2_t1_sync_progdelay_cdelay_reg <= wr_dat_d0(6 downto 0);
rf2_t1_sync_progdelay_fdelay_reg <= wr_dat_d0(10 downto 7);
rf2_t1_sync_progdelay_odelay_reg <= wr_dat_d0(15 downto 11);
end if;
rf2_t1_sync_progdelay_wack <= rf2_t1_sync_progdelay_wreq;
end if;
......@@ -446,7 +456,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, rf_trigger_ff_delay_reg, rf1_common_mixer_en_reg, rf1_common_mux_sel_reg, rf1_common_iqdac_reset_reg, rf1_common_start_lpbk_reg, rf1_t1_sync_progdelay_cdelay_reg, rf1_t1_sync_progdelay_fdelay_reg, rf1_ch_0_csr_delay_oen_reg, rf1_ch_0_csr_mux_sel_reg, rf1_ch_0_csr_trig_rst_reg, rf1_ch_0_csr_delay_latch_reg, rf1_ch_1_csr_delay_oen_reg, rf1_ch_1_csr_mux_sel_reg, rf1_ch_1_csr_trig_rst_reg, rf1_ch_1_csr_delay_latch_reg, rf2_common_mixer_en_reg, rf2_common_mux_sel_reg, rf2_common_iqdac_reset_reg, rf2_common_start_lpbk_reg, rf2_t1_sync_progdelay_cdelay_reg, rf2_t1_sync_progdelay_fdelay_reg, rf2_ch_0_csr_delay_oen_reg, rf2_ch_0_csr_mux_sel_reg, rf2_ch_0_csr_trig_rst_reg, rf2_ch_0_csr_delay_latch_reg, rf2_ch_1_csr_delay_oen_reg, rf2_ch_1_csr_mux_sel_reg, rf2_ch_1_csr_trig_rst_reg, rf2_ch_1_csr_delay_latch_reg) begin
process (adr_int, rd_req_int, rf_trigger_ff_delay_reg, rf1_common_mixer_en_reg, rf1_common_mux_sel_reg, rf1_common_iqdac_reset_reg, rf1_common_start_lpbk_reg, rf1_t1_sync_progdelay_cdelay_reg, rf1_t1_sync_progdelay_fdelay_reg, rf1_t1_sync_progdelay_odelay_reg, rf1_ch_0_csr_delay_oen_reg, rf1_ch_0_csr_mux_sel_reg, rf1_ch_0_csr_trig_rst_reg, rf1_ch_0_csr_delay_latch_reg, rf1_ch_1_csr_delay_oen_reg, rf1_ch_1_csr_mux_sel_reg, rf1_ch_1_csr_trig_rst_reg, rf1_ch_1_csr_delay_latch_reg, rf2_common_mixer_en_reg, rf2_common_mux_sel_reg, rf2_common_iqdac_reset_reg, rf2_common_start_lpbk_reg, rf2_t1_sync_progdelay_cdelay_reg, rf2_t1_sync_progdelay_fdelay_reg, rf2_t1_sync_progdelay_odelay_reg, rf2_ch_0_csr_delay_oen_reg, rf2_ch_0_csr_mux_sel_reg, rf2_ch_0_csr_trig_rst_reg, rf2_ch_0_csr_delay_latch_reg, rf2_ch_1_csr_delay_oen_reg, rf2_ch_1_csr_mux_sel_reg, rf2_ch_1_csr_trig_rst_reg, rf2_ch_1_csr_delay_latch_reg) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case adr_int(4 downto 1) is
......@@ -467,7 +477,7 @@ begin
rd_ack_d0 <= rd_req_int;
rd_dat_d0(6 downto 0) <= rf1_t1_sync_progdelay_cdelay_reg;
rd_dat_d0(10 downto 7) <= rf1_t1_sync_progdelay_fdelay_reg;
rd_dat_d0(15 downto 11) <= (others => '0');
rd_dat_d0(15 downto 11) <= rf1_t1_sync_progdelay_odelay_reg;
when "0110" =>
-- Reg rf1_ch_0_csr
rd_ack_d0 <= rd_req_int;
......@@ -497,7 +507,7 @@ begin
rd_ack_d0 <= rd_req_int;
rd_dat_d0(6 downto 0) <= rf2_t1_sync_progdelay_cdelay_reg;
rd_dat_d0(10 downto 7) <= rf2_t1_sync_progdelay_fdelay_reg;
rd_dat_d0(15 downto 11) <= (others => '0');
rd_dat_d0(15 downto 11) <= rf2_t1_sync_progdelay_odelay_reg;
when "1010" =>
-- Reg rf2_ch_0_csr
rd_ack_d0 <= rd_req_int;
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ ec477a91
-- Do not edit. Generated on Mon Mar 15 17:22:44 2021 by jgill
-- Do not edit. Generated on Wed Mar 24 16:37:32 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ ec477a91
-- Do not edit. Generated on Mon Mar 15 17:22:43 2021 by jgill
-- Do not edit. Generated on Wed Mar 24 16:37:31 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ ec477a91
-- Do not edit. Generated on Mon Mar 15 17:22:44 2021 by jgill
-- Do not edit. Generated on Wed Mar 24 16:37:32 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......
hdl/rtl/vtu_blk.vhd
View file @ ec477a91
This diff is collapsed.
hdl/rtl/wr2rf_regs_core.vhd
View file @ ec477a91
......@@ -203,7 +203,8 @@ entity wr2rf_regs_core is
rf1_t2_delay_latch_o : out std_logic;
rf1_start_lpbk_o : out std_logic;
rf1_t1_sync_cdelay_o : out std_logic_vector(6 downto 0);
rf1_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf1_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf1_t1_sync_odelay_o : out std_logic_vector(4 downto 0);
-- RF 2
rf2_mux_sel_o : out std_logic_vector(1 downto 0);
......@@ -221,7 +222,8 @@ entity wr2rf_regs_core is
rf2_t2_delay_latch_o : out std_logic;
rf2_start_lpbk_o : out std_logic;
rf2_t1_sync_cdelay_o : out std_logic_vector(6 downto 0);
rf2_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf2_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf2_t1_sync_odelay_o : out std_logic_vector(4 downto 0);
rf_trig_ff_delay_o : out std_logic_vector(9 downto 0);
......@@ -334,8 +336,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0001_00_00",
init_hwinfo_memMapVersion_i => x"0001_00_00",
init_hwinfo_firmwareVersion_i => x"0000_05_00",
init_hwinfo_memMapVersion_i => x"0000_05_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......@@ -581,7 +583,8 @@ begin
rf1_common_iqdac_reset_o => rf1_iqdac_reset_o,
rf1_common_start_lpbk_o => rf1_start_lpbk_o,
rf1_t1_sync_progdelay_cdelay_o => rf1_t1_sync_cdelay_o,
rf1_t1_sync_progdelay_fdelay_o => rf1_t1_sync_fdelay_o,
rf1_t1_sync_progdelay_fdelay_o => rf1_t1_sync_fdelay_o,
rf1_t1_sync_progdelay_odelay_o => rf1_t1_sync_odelay_o,
rf1_ch_0_csr_delay_oen_o => rf1_t1_delay_oen_o,
rf1_ch_0_csr_mux_sel_o => rf1_t1_mux_sel_o,
rf1_ch_0_csr_trig_rst_o => rf1_t1_rst_o,
......@@ -595,7 +598,8 @@ begin
rf2_common_iqdac_reset_o => rf2_iqdac_reset_o,
rf2_common_start_lpbk_o => rf2_start_lpbk_o,
rf2_t1_sync_progdelay_cdelay_o => rf2_t1_sync_cdelay_o,
rf2_t1_sync_progdelay_fdelay_o => rf2_t1_sync_fdelay_o,
rf2_t1_sync_progdelay_fdelay_o => rf2_t1_sync_fdelay_o,
rf2_t1_sync_progdelay_odelay_o => rf2_t1_sync_odelay_o,
rf2_ch_0_csr_delay_oen_o => rf2_t1_delay_oen_o,
rf2_ch_0_csr_mux_sel_o => rf2_t1_mux_sel_o,
rf2_ch_0_csr_trig_rst_o => rf2_t1_rst_o,
......
hdl/rtl/wr2rf_rftrigger.vhd
View file @ ec477a91
......@@ -61,6 +61,7 @@ entity wr2rf_rftrigger is
-- Programmable delay signals for the sync pulse into trigger unit 1
rf_t1_sync_cdelay_i : in std_logic_vector(6 downto 0);
rf_t1_sync_fdelay_i : in std_logic_vector(3 downto 0);
rf_t1_sync_odelay_i : in std_logic_vector(4 downto 0);
rf_nco_reset_cdelayed_o : out std_logic;
rf_t1_clk_p_i : in std_logic;
......@@ -96,14 +97,13 @@ end entity;
architecture rtl of wr2rf_rftrigger is
signal rf_clk_in : std_logic;
signal clk_rf : std_logic;
signal rf_clk_io : std_logic;
signal clk_vtu : std_logic;
signal rf_idelay_rdy : std_logic;
signal rf_sync : std_logic;
signal rf_t1_out : std_logic;
signal rf_t1_fb : std_logic;
......@@ -147,31 +147,17 @@ architecture rtl of wr2rf_rftrigger is
signal t1_sync_cdelayed_r : std_logic;
signal t1_sync_cdelayed_h : std_logic;
signal t1_sync_cdelayed_hh : std_logic;
signal t1_sync_cdelayed_hhh : std_logic;
signal t1_sync_cdelayed_hhh : std_logic;
signal t1_sync_pattern : std_logic_vector(23 downto 0);
signal t1_sync_base_pattern : std_logic_vector(23 downto 0) := X"0000FF";
signal t1_sync_pattern_r : std_logic_vector(23 downto 0);
signal t1_sync_fdelay : std_logic_vector(7 downto 0);
signal t1_sync_fdelay_r : std_logic_vector(7 downto 0);
signal t1_sync_fdelayed : std_logic;
signal t1_sync_fdelayed : std_logic;
signal t1_sync_odelayed : std_logic;
signal rf_sync_fb : std_logic;
-- ddr
signal didx : unsigned(2 downto 0);
signal didxp1 : unsigned(2 downto 0);
signal didx_r : unsigned(2 downto 0);
signal didxp1_r : unsigned(2 downto 0);
signal ddrdata : std_logic_vector(7 downto 0);
signal ddrdata_r : std_logic_vector(7 downto 0);
signal clkcnt125 : unsigned(0 downto 0);
signal clkcnt125_r : unsigned(0 downto 0);
signal clkcnt500 : unsigned(1 downto 0);
signal clkcnt500_r : unsigned(1 downto 0);
signal d1 : std_logic;
signal d2 : std_logic;
signal d1_r : std_logic;
signal d2_r : std_logic;
signal rf_t1_sync_x8_fb : std_logic_vector(7 downto 0);
attribute async_reg : string;
attribute async_reg of async_cdc_rst_rf_n_r : signal is "true";
......@@ -205,7 +191,7 @@ begin
-- Sync nco_reset into the VTU clk domain
process (clk_vtu, rst_rf_r) is
begin
if (rst_rf_r = '1') then
if rst_rf_r = '1' then
async_cdc_rst_rf_n_r <= '0';
cdc_rst_rf_n_r <= '0';
elsif rising_edge (clk_vtu) then
......@@ -213,6 +199,7 @@ begin
cdc_rst_rf_n_r <= async_cdc_rst_rf_n_r;
end if;
end process;
process (clk_vtu) is
begin
if rising_edge (clk_vtu) then
......@@ -221,9 +208,8 @@ begin
end if;
end process;
-- Distribute to the region for logic (vtu). Note: divided by 8.
inst_rf_clk_BUFR: BUFR
inst_rf_clkdiv_BUFR: BUFR
generic map (
BUFR_DIVIDE => "8",
SIM_DEVICE => "7SERIES")
......@@ -233,8 +219,17 @@ begin
CLR => '0',
I => rf_clk_in );
inst_rf_clk_BUFR: BUFR
generic map (
SIM_DEVICE => "7SERIES")
port map (
O => clk_rf,
CE => '1',
CLR => '0',
I => rf_clk_in );
-- The RF sync signal into the trigger unit has a programmable delay
-- It consists of a course delay circuit which is just a delayed nco_reset
-- It consists of a coarse delay circuit which is just a delayed nco_reset
-- for sys clock cycles (16 ns). Then we use an oserdes block to delay the output
-- with finer precision (1 ns). There are some odelay and idelay cells
-- but the dynamic range is insufficient to cover our needs.
......@@ -318,18 +313,42 @@ begin
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' ); -- 1-bit input: 3-state clock enable
TCE => '0' ); -- 1-bit input: 3-state clock enable
--
inst_sync_ODELAYE2 : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
DELAY_SRC => "ODATAIN", -- Delay input (ODATAIN, CLKIN)
HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
ODELAY_TYPE => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
ODELAY_VALUE => 0, -- Output delay tap setting (0-31)
PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
SIGNAL_PATTERN => "DATA" ) -- DATA, CLOCK input signal
port map (
CNTVALUEOUT => open, -- output: Counter value output
DATAOUT => t1_sync_odelayed, -- output: Delayed data/clock output
C => clk125m_i, -- input: Clock input
CE => '0', -- input: Active high enable increment/decrement input
CINVCTRL => '0', -- input: Dynamic clock inversion input
CLKIN => '0', -- input: Clock delay input
CNTVALUEIN => rf_t1_sync_odelay_i,-- input: Counter value input
INC => '0', -- input: Increment / Decrement tap delay input
LD => '1', -- input: Loads ODELAY_VALUE tap delay in VARIABLE mode
LDPIPEEN => '0', -- input: Enables the pipeline register to load data
ODATAIN => t1_sync_fdelayed, -- input: Output delay data input
REGRST => rst_sys_i ); -- input: Active-high reset tap-delay input
rf_sync_OBUFDS : IOBUFDS
generic map (
IOSTANDARD => "LVDS",
SLEW => "SLOW" )
SLEW => "FAST" )
port map (
IO => rf_t1_sync_p_o, -- Diff_p output
IOB => rf_t1_sync_n_o, -- Diff_n output
IO => rf_t1_sync_p_o,
IOB => rf_t1_sync_n_o,
T => sync_serdes_tristate,
O => rf_sync_fb,
I => t1_sync_fdelayed );
I => t1_sync_odelayed );
process (clk_sys_i)
begin
......@@ -340,6 +359,8 @@ begin
end process;
rf_t1_i : entity work.vtu_blk
generic map (
trigger_unit_t1 => true )
port map (
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
......@@ -347,9 +368,12 @@ begin
wb_i => t1_wb_in,
wb_o => t1_wb_out,
clk_rf_i => rf_clk_io,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
clk_vtu_i => clk_vtu,
sync_i => rf_sync_fb,
sync_x8_fb_i => X"00",
sync_x8_fb_o => rf_t1_sync_x8_fb,
trig_o => rf_t1_out,
trig_rst_i => rf_t1_rst_i,
trig_rst_p_o => rf_t1_rst_p_o,
......@@ -362,24 +386,27 @@ begin
rf_trig_OBUFDS : OBUFDS
generic map (
IOSTANDARD => "LVDS",
SLEW => "SLOW")
SLEW => "FAST")
port map (
O => rf_t1_p_o, -- Diff_p output
OB => rf_t1_n_o, -- Diff_n output
I => rf_t1_out );
-- Feedback (directly from the pad) of unit 1 output.
rf_trig_IBUFDS : IBUFDS
generic map (
DIFF_TERM => FALSE, --Differential Termination
IBUF_LOW_PWR => TRUE, --Lowpower (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS")
port map (
I => rf_t1_p_o, -- Diff_p output
IB => rf_t1_n_o, -- Diff_n output
O => rf_t1_fb);
--rf_trig_IBUFDS : IBUFDS
-- generic map (
-- DIFF_TERM => FALSE, --Differential Termination
-- IBUF_LOW_PWR => TRUE, --Lowpower (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS")
-- port map (
-- I => rf_t1_p_o, -- Diff_p output
-- IB => rf_t1_n_o, -- Diff_n output
-- O => open );
rf_t1_fb <= '0';
rf_t2_i : entity work.vtu_blk
generic map (
trigger_unit_t1 => false )
port map (
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
......@@ -387,9 +414,12 @@ begin
wb_i => t2_wb_in,
wb_o => t2_wb_out,
clk_rf_i => rf_clk_io,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
clk_vtu_i => clk_vtu,
sync_i => rf_t1_fb,
sync_x8_fb_i => rf_t1_sync_x8_fb,
sync_x8_fb_o => open,
trig_o => rf_t2_out,
trig_rst_i => rf_t2_rst_i,
trig_rst_p_o => rf_t2_rst_p_o,
......
hdl/rtl/x8oddr.vhd 0 → 100644
View file @ ec477a91
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity x8oddr is
port (
clk_rf_io_i : in std_logic;
clk_rf_i : in std_logic;
rst_rf_n_i : in std_logic;
clk_vtu_i : in std_logic;
rst_vtu_n_i : in std_logic;
data_out_i : in std_logic_vector(7 downto 0);
hc_delay_i : in std_logic;
ddr_data_o : out std_logic;
dbg_o : out std_logic_vector(15 downto 0) );
end entity;
architecture rtl of x8oddr is
-- ddr
signal didx : unsigned(3 downto 0);
signal didxp1 : unsigned(3 downto 0);
signal clkcntrf : unsigned(2 downto 0);
signal clkcntrf_r : unsigned(2 downto 0) := (others => '0');
signal d1out : std_logic;
signal d2out : std_logic;
signal d1out_r : std_logic;
signal d2out_r : std_logic;
-- mode signals
signal hc_delay_r : std_logic;
signal data_out_clean : std_logic_vector(7 downto 0);
signal data_out_clean_r : std_logic_vector(7 downto 0);
signal data_x16_out_nohc : std_logic_vector(15 downto 0);
signal data_x16_out_hc : std_logic_vector(15 downto 0);
signal data_x16_out : std_logic_vector(15 downto 0);
signal data_x16_out_r : std_logic_vector(15 downto 0);
signal vtuclk_r : std_logic;
signal vtu_clk_rising_edge : std_logic;
begin
data_out_clean <= (others => '0') when rst_rf_n_i = '0' else data_out_i;
data_x16_out_nohc <= data_out_clean(0) & data_out_clean(0) &
data_out_clean(1) & data_out_clean(1) &
data_out_clean(2) & data_out_clean(2) &
data_out_clean(3) & data_out_clean(3) &
data_out_clean(4) & data_out_clean(4) &
data_out_clean(5) & data_out_clean(5) &
data_out_clean(6) & data_out_clean(6) &
data_out_clean(7) & data_out_clean(7);
data_x16_out_hc <= data_out_clean(0) & data_out_clean(1) &
data_out_clean(1) & data_out_clean(2) &
data_out_clean(2) & data_out_clean(3) &
data_out_clean(3) & data_out_clean(4) &
data_out_clean(4) & data_out_clean(5) &
data_out_clean(5) & data_out_clean(6) &
data_out_clean(6) & data_out_clean(7) &
data_out_clean(7) & data_out_clean_r(0);
data_x16_out <= data_x16_out_nohc when hc_delay_i = '0' else data_x16_out_hc;
process (clk_vtu_i) is
begin
if rising_edge(clk_vtu_i) then
data_out_clean_r <= data_out_clean;
hc_delay_r <= hc_delay_i;
data_x16_out_r <= data_x16_out;
end if;
end process;
vtu_clk_rising_edge <= '1' when vtuclk_r = '0' and clk_vtu_i = '1' else '0';
clkcntrf <= clkcntrf_r + 1 when vtu_clk_rising_edge = '0' else (others => '0');
didx <= clkcntrf & '0';
didxp1 <= clkcntrf & '1';
d1out <= data_x16_out_r(to_integer(unsigned(didx)));
d2out <= data_x16_out_r(to_integer(unsigned(didxp1)));
process (clk_rf_i) is
begin
if rising_edge(clk_rf_i) then
clkcntrf_r <= clkcntrf after 1 ns;
vtuclk_r <= clk_vtu_i after 1 ns;
d1out_r <= d1out after 1 ns;
d2out_r <= d2out after 1 ns;
end if;
end process;
oddr_inst : oddr
generic map (
ddr_clk_edge => "same_edge",
init => '0',
srtype => "async" )
port map (
D1 => d1out_r,
D2 => d2out_r,
c => clk_rf_io_i,
ce => '1',
q => ddr_data_o,
r => '0',
s => '0' );
dbg_o(2 downto 0) <= std_logic_vector(clkcntrf_r);
dbg_o(3) <= d1out_r;
dbg_o(4) <= d2out_r;
dbg_o(15 downto 5) <= X"00" & "000";
end architecture;
hdl/syn/wr2rf_vme/wr2rf_t1sync_falsepath.tcl
View file @ ec477a91
# destination path clocked with RF clock, source path clocked with WR (nco_reset)
set_false_path -to [get_pins inst_rf1_trigger/rf_t1_i/inst_ISERDESE2/DDLY]
set_false_path -to [get_pins inst_rf2_trigger/rf_t1_i/inst_ISERDESE2/DDLY]
set_false_path -to [get_pins inst_rf1_trigger/rf_t1_i/g_t1_true.inst_ISERDESE2/D]
set_false_path -to [get_pins inst_rf2_trigger/rf_t1_i/g_t1_true.inst_ISERDESE2/D]
# This is a reset cleaned up circuit, from the nco_reset sourced in the WR clock domain
# destination path clocked with RF clock, source path clocked with WR (nco_reset)
......
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @ ec477a91
......@@ -1107,13 +1107,6 @@ set_clock_groups -name async_dmtd_clkout2 -asynchronous -group {clk_dmtd_bgmux}
set_clock_groups -name async_dmtd_clkout5 -asynchronous -group {clk_dmtd_bgmux} -group {clkout5}
set_clock_groups -name async_clkout5_dmtd -asynchronous -group {clkout5} -group {clk_dmtd_bgmux}
###################################
# IOBs and bounced pad logic...
###################################
# false path the programmable fine delay into the vtu sync.
set_false_path -from [get_pins inst_rf1_trigger/inst_sync_OSERDESE2/CLK] -to [get_pins inst_rf1_trigger/rf_t1_i/inst_ISERDESE2/DDLY]
set_false_path -from [get_pins inst_rf2_trigger/inst_sync_OSERDESE2/CLK] -to [get_pins inst_rf2_trigger/rf_t1_i/inst_ISERDESE2/DDLY]
###################################
# Cleanly resample nco_reset in the RF clock domain - use a little less time than the wr cycle time
###################################
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ ec477a91
......@@ -453,9 +453,11 @@ architecture rtl of wr2rf_vme is
signal rf2_start_lpbk : std_logic;
signal rf1_t1_sync_cdelay : std_logic_vector(6 downto 0);
signal rf1_t1_sync_fdelay : std_logic_vector(3 downto 0);
signal rf1_t1_sync_fdelay : std_logic_vector(3 downto 0);
signal rf1_t1_sync_odelay : std_logic_vector(4 downto 0);
signal rf2_t1_sync_cdelay : std_logic_vector(6 downto 0);
signal rf2_t1_sync_fdelay : std_logic_vector(3 downto 0);
signal rf2_t1_sync_odelay : std_logic_vector(4 downto 0);
signal rf_trig_ff_delay : std_logic_vector(9 downto 0);
signal rf1_t1_delay_latch : std_logic;
......@@ -1277,6 +1279,7 @@ begin
rf_t1_sync_i => nco_reset_rf1_trig1,
rf_t1_sync_cdelay_i => rf1_t1_sync_cdelay,
rf_t1_sync_fdelay_i => rf1_t1_sync_fdelay,
rf_t1_sync_odelay_i => rf1_t1_sync_odelay,
rf_nco_reset_cdelayed_o => rf1_nco_reset_cdelayed,
rf_t1_sync_p_o => rf1_sync_p_o,
rf_t1_sync_n_o => rf1_sync_n_o,
......@@ -1321,6 +1324,7 @@ begin
rf_t1_sync_i => nco_reset_rf2_trig1,
rf_t1_sync_cdelay_i => rf2_t1_sync_cdelay,
rf_t1_sync_fdelay_i => rf2_t1_sync_fdelay,
rf_t1_sync_odelay_i => rf2_t1_sync_odelay,
rf_nco_reset_cdelayed_o => rf2_nco_reset_cdelayed,
rf_t1_sync_p_o => rf2_sync_p_o,
......@@ -1505,7 +1509,8 @@ begin
rf1_t1_rst_o => rf1_t1_rst,
rf1_t1_delay_latch_o => rf1_t1_delay_latch,
rf1_t1_sync_cdelay_o => rf1_t1_sync_cdelay,
rf1_t1_sync_fdelay_o => rf1_t1_sync_fdelay,
rf1_t1_sync_fdelay_o => rf1_t1_sync_fdelay,
rf1_t1_sync_odelay_o => rf1_t1_sync_odelay,
rf1_t2_delay_oen_o => rf1_t2_delay_oen_o,
rf1_t2_mux_sel_o => rf1_t2_mux_sel_o,
rf1_t2_rst_o => rf1_t2_rst,
......@@ -1521,6 +1526,7 @@ begin
rf2_t1_delay_latch_o => rf2_t1_delay_latch,
rf2_t1_sync_cdelay_o => rf2_t1_sync_cdelay,
rf2_t1_sync_fdelay_o => rf2_t1_sync_fdelay,
rf2_t1_sync_odelay_o => rf2_t1_sync_odelay,
rf2_t2_delay_oen_o => rf2_t2_delay_oen_o,
rf2_t2_mux_sel_o => rf2_t2_mux_sel_o,
rf2_t2_rst_o => rf2_t2_rst,
......
software/include/trigunit_regs.h
View file @ ec477a91
......@@ -53,23 +53,15 @@
/* Window value: number of output pulses (W) */
#define TRIGUNIT_REGS_WVALUEONLINE 0x38UL
/* Delay on the sync input */
#define TRIGUNIT_REGS_SYNCIDELAY 0x40UL
#define TRIGUNIT_REGS_SYNCIDELAY_DELAY_MASK 0x1fUL
#define TRIGUNIT_REGS_SYNCIDELAY_DELAY_SHIFT 0
/* Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay */
#define TRIGUNIT_REGS_TRIGOHCDELAY 0x42UL
#define TRIGUNIT_REGS_TRIGOHCDELAY 0x40UL
#define TRIGUNIT_REGS_TRIGOHCDELAY_SET 0x1UL
/* Delay on the trigger output */
#define TRIGUNIT_REGS_TRIGODELAY 0x44UL
#define TRIGUNIT_REGS_TRIGODELAY 0x42UL
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_MASK 0x1fUL
#define TRIGUNIT_REGS_TRIGODELAY_DELAY_SHIFT 0
/* Delay the trigger output by a fraction of the RF clock, 1/8ths - hot-1 encoded */
#define TRIGUNIT_REGS_TRIGOUTPROGDELAY 0x46UL
/* None */
#define TRIGUNIT_REGS_TRIGDIAG 0x50UL
#define TRIGUNIT_REGS_TRIGDIAG_SIZE 16 /* 0x10 */
......@@ -113,20 +105,14 @@ struct trigunit_regs {
/* [0x38]: REG (ro) Window value: number of output pulses (W) */
uint64_t wValueOnline;
/* [0x40]: REG (rw) Delay on the sync input */
uint16_t syncIDelay;
/* [0x42]: REG (rw) Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay */
/* [0x40]: REG (rw) Delay the trigger output for x 0.5 RF clock cycle, 0 = no delay, 1 = half cycle delay */
uint16_t trigOHCDelay;
/* [0x44]: REG (rw) Delay on the trigger output */
/* [0x42]: REG (rw) Delay on the trigger output */
uint16_t trigODelay;
/* [0x46]: REG (rw) Delay the trigger output by a fraction of the RF clock, 1/8ths - hot-1 encoded */
uint16_t trigOutProgDelay;
/* padding to: 20 words */
uint32_t __padding_2[2];
uint32_t __padding_2[3];
/* [0x50]: SUBMAP (no description) */
struct vtudiag_regs trigdiag;
......
software/include/wr2rf_init_regs.h
View file @ ec477a91
#ifndef __CHEBY__WR2RF_INIT_REGS__H__
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "oc_spi16_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#include "hwInfo.h"
#include "oc_spi16_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
/* RF indentification */
......
software/include/wr2rf_init_rf_ch_regs.h
View file @ ec477a91
......@@ -16,6 +16,8 @@
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_CDELAY_SHIFT 0
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_FDELAY_MASK 0x780UL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_FDELAY_SHIFT 7
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_ODELAY_MASK 0xf800UL
#define WR2RF_INIT_RF_CH_REGS_T1_SYNC_PROGDELAY_ODELAY_SHIFT 11
/* None */
#define WR2RF_INIT_RF_CH_REGS_CH 0x4UL
......
software/include/wr2rf_vme_regs.h
View file @ ec477a91
#ifndef __CHEBY__WR2RF_VME_REGS__H__
#define __CHEBY__WR2RF_VME_REGS__H__
#include "wr2rf_init_regs.h"
#include "wr2rf_ctrl_regs.h"
#include "wr2rf_init_regs.h"
#define WR2RF_VME_REGS_SIZE 32768 /* 0x8000 = 32KB */
/* Memory map for the initialization part */
......
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