10 MHz output is subject to metastability problems and cannot be aligned with PPS
The 10 MHz output has been observed to exhibit metastability problems in BA4.
The 10 MHz is derived from the system clock 62.5 MHz on the FPGA via an OSERDES and then driven onto the PCB where it is cleaned by a flip-flop. The FPGA pin is located in an high range bank therefore there isn't an ODELAY cell available to adjust the timing of the signal. This FF is clocked by the 1 GHz DDS clock from the LTC6950 PLL.
There are a few things that need to be addressed to fix this problem:
- The 10 MHz output should be moved to the high performance bank so that an ODELAY cell may be used to trim the delay into the cleaning FF
- The clock frequency for the cleaner FF should be reduced. It's too fast and gives a small window of acceptable delay that means it's much more likely to exhibit metastability issues through PVT changes.
The ODELAY cell is subject to jitter of up to 400 ps, therefore trying to hit a narrow metastability free window is much harder with such a high clock frequency.
Could we alleviate this problem on the current boards ?
We could try adjusting the phase of the 1 GHz clock used by the cleaner FF. We could sweep the phase and find the best phase offset to minimise metastability behaviour. But this also has knock-on consequences...:
- this 1GHz output is also shared with clocking the ad9910 DDS chip. Therefore changing the phase of this clock affects the behaviour of the DDS. The initialisation sequence for the AD9910 accounts for some of this behaviour but it must be manually inspected to check the internal calibration parameters chosen are optimal.
- the odelay delay value used on the sync signal to reset the phase of the DDS after receiving an nco_reset has to be recalibrated.
- it's likely that there will not be a single phase setting that is acceptable for every board. The v2 cards have been manufactured in two batches. The first batch of cards appears most likely to exhibit metastability whilst the second batch appears less likely. Therefore each batch will probably need its phase adjusted and subsequent DDS parameters recalibrated...