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IRLML2803PBF must be replaced with PMV40UN2R
#2
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
2
updated
Feb 05, 2021
Change licence to CERN-OHL-S v2
#1
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Feb 05, 2021
Optimise BOM
#12
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
5
updated
Jul 15, 2020
Replace ADCLK925 with LTC6957-2
#44
· opened
Jun 29, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
18
updated
Jul 08, 2020
Verify that the BE-RF VME crate power supplies can deliver enough current on P1
#4
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
26
updated
Jul 07, 2020
RF trigger output
#23
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
6
updated
Jul 07, 2020
Front panel connections
#24
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
5
updated
Jul 07, 2020
Should RF trigger driver be powered from P3V3A?
#45
· opened
Jun 30, 2020
by
Dimitris Lampridis
Schematic done
hw
question
CLOSED
2
updated
Jul 07, 2020
DAC clock - AC coupling
#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
Faster buffers for front panel I/O
#17
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
important
xdc update
CLOSED
7
updated
Jun 29, 2020
Series resistors and buffers on VME P0 TTL lines
#7
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
minor
xdc update
CLOSED
8
updated
Jun 29, 2020
FPGA configuration IO
#28
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
xdc update
CLOSED
2
updated
Jun 29, 2020
Address switch
#16
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
minor
xdc update
CLOSED
4
updated
Jun 29, 2020
Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
Power sequencing and consumption
#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
DC coupling for FPGA clock ECL to LVDS
#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
Front panel Timing I/O
#25
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
2
updated
Jun 24, 2020
Replace capacitors and inductors with proper symbols in RF main sheet
#9
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
4
updated
Jun 18, 2020
wire length matching
#29
· opened
May 13, 2020
by
Tristan Gingold
Schematic done
hw
minor
CLOSED
4
updated
Jun 17, 2020
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