DC coupling for FPGA clock ECL to LVDS
Do we really want AC coupled clock for FPGA from the RF part?
a ECL to LVDS (DC coupled) is easy to do with 50ohm serie resistor followed by 100ohm to GND (for both ECL outputs). It avoid to have unknown state (self triggering input stage) for FPGA logic if no clock/RF output.
Is the clock arriving on FPGA pin with internal 100 diff termination?