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Should RF trigger driver be powered from P3V3A?
#45
· opened
Jun 30, 2020
by
Dimitris Lampridis
Schematic done
hw
question
CLOSED
2
updated
Jul 07, 2020
Replace ADCLK925 with LTC6957-2
#44
· opened
Jun 29, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
18
updated
Jul 08, 2020
Missing correct symbols in rf_main sheet
#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
Use separate FPGA pins for the two WR EEPROMs
#40
· opened
May 19, 2020
by
Dimitris Lampridis
Schematic done
hdl
hw
important
xdc update
CLOSED
3
updated
Jun 29, 2020
delay line for TU
#39
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
CLOSED
3
updated
Jun 25, 2020
BOM de de-optimization
#38
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
CLOSED
1
updated
Jun 06, 2020
Power sequencing and consumption
#37
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
7
updated
Jun 29, 2020
Consider serial termination on the LEN pin of the 100EP195 delay line
#36
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
minor
CLOSED
1
updated
Jun 09, 2020
Check DDS IOUPDATE signal FPGA connection
#35
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
question
CLOSED
1
updated
Jun 09, 2020
Dielectric of ceramic capacitors in the RF path
#34
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
CLOSED
3
updated
Jun 10, 2020
Main RF generation
#33
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
3
updated
Jun 09, 2020
DAC clock - AC coupling
#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
DC coupling for FPGA clock ECL to LVDS
#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
Trigger unit output glitches
#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
wire length matching
#29
· opened
May 13, 2020
by
Tristan Gingold
Schematic done
hw
minor
CLOSED
4
updated
Jun 17, 2020
FPGA configuration IO
#28
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
xdc update
CLOSED
2
updated
Jun 29, 2020
consider using an INA240 for the OCXO current sense
#27
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
minor
CLOSED
2
updated
Jun 10, 2020
1V0 LDO current sharing scheme - questions
#26
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
question
CLOSED
8
updated
Jun 16, 2020
Front panel Timing I/O
#25
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
2
updated
Jun 24, 2020
Front panel connections
#24
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
5
updated
Jul 07, 2020
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