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White Rabbit Network Robustness
Commit c77906dc authored by Cesar Prados's avatar Cesar Prados
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hdl/linear_block_code/sim/enc_test/enc_test.cr.mti 0 → 100644
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/home/bradomyn/project/wrn-robustness/hdl/linear_block_code/syn/linear_block_encoder.vhd {1 {vcom -work work -2002 -explicit -vopt /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/syn/linear_block_encoder.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity linear_block_enc
-- Compiling architecture Behavioral of linear_block_enc
} {} {}} /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd {2 {vcom -work work -2002 -explicit -vopt /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Compiling entity linear_block_testb
-- Compiling architecture behaviour of linear_block_testb
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(47): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
} {} {}} /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_testb.vhd {2 {vcom -work work -2002 -explicit -vopt /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_testb.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Compiling entity linear_block_testb
-- Compiling architecture behaviour of linear_block_testb
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_testb.vhd(47): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
} {} {}}
hdl/linear_block_code/sim/enc_test/enc_test.mpf 0 → 100644
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hdl/linear_block_code/sim/enc_test/transcript 0 → 100644
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hdl/linear_block_code/sim/enc_test/vish_stacktrace.vstf 0 → 100644
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# Current time Tue Mar 13 13:25:40 2012
# ModelSim Stack Trace
# Program = vish
# Id = "10.0c"
# Version = "2011.07"
# Date = "Jul 21 2011"
# Platform = linux
# 0 0x0837f2a2: '<unknown (@0x837f2a2)>'
# 1 0x0837f325: '<unknown (@0x837f325)>'
# 2 0x0837730a: '<unknown (@0x837730a)>'
# 3 0x0840ce61: '<unknown (@0x840ce61)>'
# 4 0x083ff3b0: '<unknown (@0x83ff3b0)>'
# 5 0x083ff5e2: '<unknown (@0x83ff5e2)>'
# 6 0x083a639d: '<unknown (@0x83a639d)>'
# 7 0x083b7919: '<unknown (@0x83b7919)>'
# 8 0x083dd24b: '<unknown (@0x83dd24b)>'
# 9 0x083e2333: '<unknown (@0x83e2333)>'
# 10 0x083b98ac: '<unknown (@0x83b98ac)>'
# 11 0xf6f18ac0: 'Itcl_EvalMemberCode + 0x17c' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 12 0xf6f19895: 'Itcl_ExecMethod + 0xc1' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 13 0xf6f201ed: 'Itcl_EvalArgs + 0x65' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 14 0xf6f1a1ea: 'Itcl_HandleInstance + 0x17e' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 15 0x083b7919: '<unknown (@0x83b7919)>'
# 16 0x083dd24b: '<unknown (@0x83dd24b)>'
# 17 0x083e2333: '<unknown (@0x83e2333)>'
# 18 0x083b98ac: '<unknown (@0x83b98ac)>'
# 19 0xf6f18ac0: 'Itcl_EvalMemberCode + 0x17c' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 20 0xf6f19895: 'Itcl_ExecMethod + 0xc1' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 21 0xf6f201ed: 'Itcl_EvalArgs + 0x65' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 22 0xf6f1a1ea: 'Itcl_HandleInstance + 0x17e' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 23 0x083b7919: '<unknown (@0x83b7919)>'
# 24 0x083b967e: '<unknown (@0x83b967e)>'
# 25 0x083b99b1: '<unknown (@0x83b99b1)>'
# 26 0x083bcf00: '<unknown (@0x83bcf00)>'
# 27 0x083b7919: '<unknown (@0x83b7919)>'
# 28 0x083dd24b: '<unknown (@0x83dd24b)>'
# 29 0x083e2333: '<unknown (@0x83e2333)>'
# 30 0x083b98ac: '<unknown (@0x83b98ac)>'
# 31 0x083bc95d: '<unknown (@0x83bc95d)>'
# 32 0x083b7919: '<unknown (@0x83b7919)>'
# 33 0x083dd24b: '<unknown (@0x83dd24b)>'
# 34 0x083e2333: '<unknown (@0x83e2333)>'
# 35 0x083b98ac: '<unknown (@0x83b98ac)>'
# 36 0x083c697e: '<unknown (@0x83c697e)>'
# 37 0x083b7919: '<unknown (@0x83b7919)>'
# 38 0x083dd24b: '<unknown (@0x83dd24b)>'
# 39 0x083e2333: '<unknown (@0x83e2333)>'
# 40 0x083b98ac: '<unknown (@0x83b98ac)>'
# 41 0xf6f18ac0: 'Itcl_EvalMemberCode + 0x17c' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 42 0xf6f19895: 'Itcl_ExecMethod + 0xc1' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 43 0xf6f201ed: 'Itcl_EvalArgs + 0x65' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 44 0xf6f1a1ea: 'Itcl_HandleInstance + 0x17e' in '/home/bradomyn/modelsim/modeltech/linux/libitcl3.2.so'
# 45 0x083b7919: '<unknown (@0x83b7919)>'
# 46 0x083dd24b: '<unknown (@0x83dd24b)>'
# 47 0x083e2333: '<unknown (@0x83e2333)>'
# 48 0x08407b89: '<unknown (@0x8407b89)>'
# 49 0x083b7919: '<unknown (@0x83b7919)>'
# 50 0x083dd24b: '<unknown (@0x83dd24b)>'
# 51 0x083e2333: '<unknown (@0x83e2333)>'
# 52 0x08407b89: '<unknown (@0x8407b89)>'
# 53 0x083b7919: '<unknown (@0x83b7919)>'
# 54 0x083b8dad: '<unknown (@0x83b8dad)>'
# 55 0x083a49d3: '<unknown (@0x83a49d3)>'
# 56 0x083893db: '<unknown (@0x83893db)>'
# 57 0x0832838b: '<unknown (@0x832838b)>'
# 58 0x08328bc5: '<unknown (@0x8328bc5)>'
# 59 0x083ff3b0: '<unknown (@0x83ff3b0)>'
# 60 0x083ff5e2: '<unknown (@0x83ff5e2)>'
# 61 0x08328c89: '<unknown (@0x8328c89)>'
# 62 0x0832fe5c: '<unknown (@0x832fe5c)>'
# 63 0x08192c62: '<unknown (@0x8192c62)>'
# 64 0x08194c0b: '<unknown (@0x8194c0b)>'
# 65 0xf734647e: '_libc_start_main + 0xee' in '/usr/lib32/libc.so.6'
# End of Stack Trace
hdl/linear_block_code/sim/enc_test/work/@_opt/vopteivcv3 0 → 100644
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=13-bc305be2d7c8-4f5f4bbf-cc58-684
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=14-bc305be2d7c8-4f5f7d72-97b5c-83f
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l0
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity linear_block_performance is
end linear_block_performance;
architecture behaviour of linear_block_performance is
signal clk :std_logic := '0';
signal data :std_logic_vector (11 downto 0) := (others => '0');
signal word :std_logic_vector (23 downto 0) := (others => '0');
signal frame:std_logic_vector (120000 downto 0) := (others => '0');
signal data_1,data_2,data_3,data_4,data_5 :std_logic_vector(11 downto 0);
signal word_1,word_2,word_3,word_4, word_5 :std_logic_vector(23 downto 0);
shared variable count : integer := 0;
constant PERIOD : time := 8 ns;
constant payload: integer := 1;
constant numEncoder : integer := 5;
constant sizeword : integer := 12;
constant lengthframe: integer := 6000;
constant zeros : std_logic_vector(23 downto 0) := (others => '0');
component linear_block_enc
port(
clk : in std_logic;
data_in: in std_logic_vector(11 downto 0);
encoded_out:out std_logic_vector(23 downto 0)
);
end component;
begin
encoder_1: linear_block_enc
port map(
clk => clk,
data_in => data_1,
encoded_out => word_1
);
encoder_2: linear_block_enc
port map(
clk => clk,
data_in => data_2,
encoded_out => word_2
);
encoder_3: linear_block_enc
port map(
clk => clk,
data_in => data_3,
encoded_out => word_3
);
encoder_4: linear_block_enc
port map(
clk => clk,
data_in => data_4,
encoded_out => word_4
);
encoder_5: linear_block_enc
port map(
clk => clk,
data_in => data_5,
encoded_out => word_5
);
clk_proc: process
begin
clk <= '1';
wait for PERIOD/2;
clk <= '0';
wait for PERIOD/2;
end process;
data_proc: process(clk)
begin
if(count < lengthframe) then
data_1 <= to_stdlogicvector(x"111");
data_2 <= to_stdlogicvector(x"111");
data_3 <= to_stdlogicvector(x"111");
data_4 <= to_stdlogicvector(x"111");
data_5 <= to_stdlogicvector(x"111");
count := count + (numEncoder*sizeword);
else
data_1 <= zeros(11 downto 0);
data_2 <= zeros(11 downto 0);
data_3 <= zeros(11 downto 0);
data_4 <= zeros(11 downto 0);
data_5 <= zeros(11 downto 0);
end if;
end process;
frame_proc: process(clk)
begin
if(count < lengthframe) then
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
word_5 & word_4 & word_3 & word_2 & word_1;
else
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
zeros & zeros & zeros & zeros & zeros;
end if;
end process;
end;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity linear_block_testb is
end linear_block_testb;
architecture behaviour of linear_block_testb is
signal clk :std_logic := '0';
signal data :std_logic_vector (11 downto 0) := (others => '0');
signal word :std_logic_vector (23 downto 0) := (others => '0');
constant PERIOD : time := 8 ns;
component linear_block_enc
port(
clk : in std_logic;
data_in: in std_logic_vector(11 downto 0);
encoded_out:out std_logic_vector(23 downto 0)
);
end component;
begin
encoder: linear_block_enc
port map(
clk => clk,
data_in => data,
encoded_out => word
);
clk_proc: process
begin
clk <= '1';
wait for PERIOD/2;
clk <= '0';
wait for PERIOD/2;
end process;
data_proc: process
begin
wait for 16 ns;
data <= to_stdlogicvector(x"555");
wait;
end process;
end;
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/home/bradomyn/project/wrn-robustness/hdl/linear_block_code/syn/linear_block_encoder.vhd {1 {vcom -work work -2002 -explicit -vopt /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/syn/linear_block_encoder.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity linear_block_enc
-- Compiling architecture Behavioral of linear_block_enc
} {} {}} /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd {2 {vcom -work work -2002 -explicit -vopt /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Compiling entity linear_block_performance
-- Compiling architecture behaviour of linear_block_performance
** Warning: /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(18): (vcom-1236) Shared variables must be of a protected type.
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(80): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(81): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(82): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(83): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
** Warning: [10] /home/bradomyn/project/wrn-robustness/hdl/linear_block_code/sim/linear_block_performance.vhd(84): (vcom-1143) Ambiguous parameter type to function 'To_StdLogicVector'.
Expression is illegal VHDL-1993 but legal VHDL-1987.
Suggest use of qualified expressions or VHDL-1987.
} {} {}}
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