Commit 1d24ecfb authored by Alessandro Rubini's avatar Alessandro Rubini

Remove all spaces at end-of-line

If you find this patch with "git blame" please use "git blame -w"
to have all white-space ignored while associating lines to commits.

This commit has no practical effect but cleanup. I made it
with sed like this:

  git grep -l '[ \t]$' | xargs sed -i 's/[ \t]*$//'

However, I had to manually restore doc/wrpc_mon.png after the fact.
Similarly, I restored the include/hw/*regs.h files, as they
are (most likely) auto-generated.
parent 11c623d7
# choose your board here.
# choose your board here.
BOARD = spec
# 1 enables Etherbone support
......@@ -81,8 +81,8 @@ OBJS_PTPD = $(PTP_NOPOSIX)/PTPWRd/arith.o \
$(PTP_NOPOSIX)/libposix/net.o \
$(PTP_NOPOSIX)/softpll/softpll_ng.o
CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled
LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -nostdlib -T arch/lm32/ram.ld
CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled
LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -nostdlib -T arch/lm32/ram.ld
OBJS_PLATFORM=arch/lm32/crt0.o arch/lm32/irq.o arch/lm32/debug.o
......@@ -96,14 +96,14 @@ CC=$(CROSS_COMPILE)gcc
OBJDUMP=$(CROSS_COMPILE)objdump
OBJCOPY=$(CROSS_COMPILE)objcopy
SIZE=$(CROSS_COMPILE)size
CFLAGS= $(CFLAGS_PLATFORM) $(CFLAGS_EB) $(CFLAGS_PTPD) $(INCLUDE_DIRS) -ffunction-sections -fdata-sections -Os -Iinclude -include include/trace.h $(PTPD_CFLAGS) -I$(PTP_NOPOSIX)/PTPWRd -I. -Isoftpll
LDFLAGS= $(LDFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Wl,--gc-sections -Os -Iinclude
OBJS=$(OBJS_PLATFORM) $(OBJS_WRC) $(OBJS_PTPD) $(OBJS_SHELL) $(OBJS_TESTS) $(OBJS_LIB) $(OBJS_SOCKITOWM) $(OBJS_SOFTPLL) $(OBJS_DEV)
OUTPUT=wrc
REVISION=$(shell git rev-parse HEAD)
$(shell ln -sf ../boards/$(BOARD)/board.h include/board.h)
$(shell ln -sf ../boards/$(BOARD)/board.h include/board.h)
all: tools wrc
......@@ -112,14 +112,14 @@ wrc: $(OBJS)
echo "const char *build_date = __DATE__ \" \" __TIME__;" >> revision.c
$(CC) $(CFLAGS) -c revision.c
$(SIZE) -t $(OBJS)
${CC} -o $(OUTPUT).elf revision.o $(OBJS) $(LDFLAGS)
${CC} -o $(OUTPUT).elf revision.o $(OBJS) $(LDFLAGS)
${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -d $(OUTPUT).elf > $(OUTPUT)_disasm.S
cd tools; $(MAKE)
./tools/genraminit $(OUTPUT).bin 0 > $(OUTPUT).ram
./tools/genramvhd -s 90112 $(OUTPUT).bin > $(OUTPUT).vhd
clean:
clean:
rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram
%.o: %.c
......
......@@ -3,7 +3,7 @@
* Load this code anywhere in memory and point DEBA at it.
* When DC=1 it chain loads the exception handlers at EBA.
* User exception handlers must save to the stack.
*
*
* Copyright (C) 2011 by Wesley W. Terpstra <w.terpstra@gsi.de>
*/
......@@ -289,7 +289,7 @@ handle_debug_trap:
calli jtag_put_byte
_get_command:
/* Input: [Wxxxxxxx]
/* Input: [Wxxxxxxx]
* W=0, x=0: quit debug trap
* W=1, x=0: report register dump location
* W=0, x>0: read 'x' bytes
......@@ -306,7 +306,7 @@ _get_command:
/* Load memory access address */
calli jtag_get_word
mv r11, r1
/* Either read or write */
bne r10, r0, _read_mem
......
......@@ -38,7 +38,7 @@ SECTIONS
{
.boot : { *(.boot) } > ram
/* Code */
.text :
{
......@@ -60,26 +60,26 @@ SECTIONS
KEEP (*(.dtors))
KEEP (*(.jcr))
_etext = .;
} > ram =0
} > ram =0
/* Exception handlers */
.eh_frame_hdr : { *(.eh_frame_hdr) } > ram
.eh_frame : { KEEP (*(.eh_frame)) } > ram
.gcc_except_table : { *(.gcc_except_table) *(.gcc_except_table.*) } > ram
/* Read-only data */
.rodata :
{
.rodata :
{
. = ALIGN(4);
_frodata = .;
_frodata_rom = LOADADDR(.rodata);
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
/* Data */
.data :
.data :
{
. = ALIGN(4);
_fdata = .;
......@@ -90,8 +90,8 @@ SECTIONS
_gp = ALIGN(16) + 0x7ff0;
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
} > ram
/* BSS */
.bss :
{
......@@ -108,10 +108,10 @@ SECTIONS
_end = .;
PROVIDE (end = .);
} > ram
/* First location in stack is highest address in RAM */
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
......@@ -120,7 +120,7 @@ SECTIONS
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
......
......@@ -10,7 +10,7 @@ void dna_read(uint32_t *lo, uint32_t *hi)
{
uint64_t dna = 0;
int i;
gpio_out(DNA_DATA, 0);
delay(10);
gpio_out(DNA_CLK, 0);
......@@ -19,7 +19,7 @@ void dna_read(uint32_t *lo, uint32_t *hi)
delay(10);
gpio_out(DNA_SHIFT, 0);
delay(10);
delay(10);
gpio_out(DNA_CLK, 1);
delay(10);
......@@ -31,7 +31,7 @@ void dna_read(uint32_t *lo, uint32_t *hi)
gpio_out(DNA_SHIFT, 1);
delay(10);
for(i=0;i<57;i++)
{
dna <<= 1;
......@@ -44,7 +44,7 @@ void dna_read(uint32_t *lo, uint32_t *hi)
gpio_out(DNA_CLK, 0);
delay(10);
}
*hi = (uint32_t) (dna >> 32);
*lo = (uint32_t) dna;
}
......@@ -5,8 +5,8 @@
#include "syscon.h"
/*
* The SFP section is placed somewhere inside FMC EEPROM and it really does not
* matter where (can be a binary data inside the Board Info section but can be
* The SFP section is placed somewhere inside FMC EEPROM and it really does not
* matter where (can be a binary data inside the Board Info section but can be
* placed also outside the FMC standardized EEPROM structure. The only requirement
* is that it starts with 0xdeadbeef pattern. The structure of SFP section is:
*
......@@ -23,10 +23,10 @@
* --------------------------------------------------------------------------------------------
*
* Fields description:
* cal_ph_trans - t2/t4 phase transition value (got from measure_t24p() ), contains
* cal_ph_trans - t2/t4 phase transition value (got from measure_t24p() ), contains
* _valid_ bit (MSB) and 31 bits of cal_phase_transition value
* count - how many SFPs are described in the list (binary)
* SFP(n) part number - SFP PN as read from SFP's EEPROM (e.g. AXGE-1254-0531)
* SFP(n) part number - SFP PN as read from SFP's EEPROM (e.g. AXGE-1254-0531)
* (16 ascii chars)
* checksum - low order 8 bits of the sum of all bytes for the SFP(PN,alpha,dTx,dRx)
*
......@@ -49,7 +49,7 @@ uint8_t has_eeprom = 0;
uint8_t eeprom_present(uint8_t i2cif, uint8_t i2c_addr)
{
has_eeprom = 1;
has_eeprom = 1;
if( !mi2c_devprobe(i2cif, i2c_addr) )
if( !mi2c_devprobe(i2cif, i2c_addr) )
has_eeprom = 0;
......@@ -151,7 +151,7 @@ int32_t eeprom_get_sfp(uint8_t i2cif, uint8_t i2c_addr, struct s_sfpinfo* sfp, u
if(!add)
{
if( eeprom_read(i2cif, i2c_addr, EE_BASE_SFP + sizeof(sfpcount) + pos*sizeof(struct s_sfpinfo), (uint8_t*)sfp,
if( eeprom_read(i2cif, i2c_addr, EE_BASE_SFP + sizeof(sfpcount) + pos*sizeof(struct s_sfpinfo), (uint8_t*)sfp,
sizeof(struct s_sfpinfo)) != sizeof(struct s_sfpinfo) )
return EE_RET_I2CERR;
......@@ -184,16 +184,16 @@ int8_t eeprom_match_sfp(uint8_t i2cif, uint8_t i2c_addr, struct s_sfpinfo* sfp)
struct s_sfpinfo dbsfp;
for(i=0; i<sfpcount; ++i)
{
temp = eeprom_get_sfp(WRPC_FMC_I2C, FMC_EEPROM_ADR, &dbsfp, 0, i);
if(!i)
{
{
temp = eeprom_get_sfp(WRPC_FMC_I2C, FMC_EEPROM_ADR, &dbsfp, 0, i);
if(!i)
{
sfpcount=temp; //only in first round valid sfpcount is returned from eeprom_get_sfp
if(sfpcount == 0 || sfpcount == 0xFF)
return 0;
else if(sfpcount<0)
else if(sfpcount<0)
return sfpcount;
}
}
if( !strncmp(dbsfp.pn, sfp->pn, 16) )
{
sfp->dTx = dbsfp.dTx;
......@@ -201,7 +201,7 @@ int8_t eeprom_match_sfp(uint8_t i2cif, uint8_t i2c_addr, struct s_sfpinfo* sfp)
sfp->alpha = dbsfp.alpha;
return 1;
}
}
}
return 0;
}
......@@ -256,7 +256,7 @@ int8_t eeprom_init_purge(uint8_t i2cif, uint8_t i2c_addr)
return used;
}
/*
/*
* Appends a new shell command at the end of boot script
*/
int8_t eeprom_init_add(uint8_t i2cif, uint8_t i2c_addr, const char *args[])
......@@ -302,7 +302,7 @@ int32_t eeprom_init_show(uint8_t i2cif, uint8_t i2c_addr)
if( eeprom_read(i2cif, i2c_addr, EE_BASE_INIT, (uint8_t*)&used, sizeof(used)) != sizeof(used) )
return EE_RET_I2CERR;
if(used==0 || used==0xffff)
if(used==0 || used==0xffff)
{
used = 0; //this means the memory is blank
mprintf("Empty init script...\n");
......@@ -325,7 +325,7 @@ int8_t eeprom_init_readcmd(uint8_t i2cif, uint8_t i2c_addr, char* buf, uint8_t b
static uint16_t used = 0;
uint8_t i=0;
if(next == 0)
if(next == 0)
{
if( eeprom_read(i2cif, i2c_addr, EE_BASE_INIT, (uint8_t*)&used, sizeof(used)) != sizeof(used) )
return EE_RET_I2CERR;
......
/*
WR Endpoint (WR-compatible Ethernet MAC driver
WR Endpoint (WR-compatible Ethernet MAC driver
Tomasz Wlostowski/CERN 2011
......@@ -63,8 +63,8 @@ void get_mac_addr(uint8_t dev_addr[])
{
dev_addr[5] = (EP->MACL & 0x000000ff);
dev_addr[4] = (EP->MACL & 0x0000ff00) >> 8;
dev_addr[3] = (EP->MACL & 0x00ff0000) >> 16;
dev_addr[2] = (EP->MACL & 0xff000000) >> 24;
dev_addr[3] = (EP->MACL & 0x00ff0000) >> 16;
dev_addr[2] = (EP->MACL & 0xff000000) >> 24;
dev_addr[1] = (EP->MACH & 0x000000ff);
dev_addr[0] = (EP->MACH & 0x0000ff00) >> 8;
}
......@@ -85,7 +85,7 @@ void ep_init(uint8_t mac_addr[])
EP->TSCR = EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS; /* Enable timestamping */
/* Configure DMTD phase tracking */
EP->DMCR = EP_DMCR_EN | EP_DMCR_N_AVG_W(DMTD_AVG_SAMPLES);
EP->DMCR = EP_DMCR_EN | EP_DMCR_N_AVG_W(DMTD_AVG_SAMPLES);
}
/* Enables/disables transmission and reception. When autoneg is set to 1,
......@@ -153,9 +153,9 @@ int ep_link_up(uint16_t *lpa)
/* Returns the TX/RX latencies. They are valid only when the link is up. */
int ep_get_deltas(uint32_t *delta_tx, uint32_t *delta_rx)
{
/* fixme: these values should be stored in calibration block in the EEPROM on the FMC. Also, the TX/RX delays of a particular SFP
/* fixme: these values should be stored in calibration block in the EEPROM on the FMC. Also, the TX/RX delays of a particular SFP
should be added here */
*delta_tx = sfp_deltaTx;
*delta_tx = sfp_deltaTx;
*delta_rx = sfp_deltaRx + PICOS_PER_SERIAL_BIT * MDIO_WR_SPEC_BSLIDE_R(pcs_read(MDIO_REG_WR_SPEC));
return 0;
}
......@@ -164,7 +164,7 @@ int ep_get_deltas(uint32_t *delta_tx, uint32_t *delta_rx)
int ep_cal_pattern_enable()
{
uint32_t val;
val = pcs_read(MDIO_REG_WR_SPEC);
val = pcs_read(MDIO_REG_WR_SPEC);
val |= MDIO_WR_SPEC_TX_CAL;
pcs_write(MDIO_REG_WR_SPEC, val);
......
/* Endpoint Packet Filter/Classifier driver
/* Endpoint Packet Filter/Classifier driver
A little explanation: The WR core needs to classify the incoming packets into
two (or more categories):
......@@ -6,11 +6,11 @@
- Other packets matching user's provided pattern, which shall go to the external fabric
port - for example to Etherbone, host network controller, etc.
- packets to be dropped (used neither by the WR Core or the user application)
WR Endpoint (WR MAC) inside the WR Core therefore contains a simple microprogrammable
packet filter/classifier. The classifier processes the incoming packet, and assigns it
to one of 8 classes (an 8-bit word, where each bit corresponds to a particular class) or
eventually drops it. Hardware implementation of the unit is a simple VLIW processor with
to one of 8 classes (an 8-bit word, where each bit corresponds to a particular class) or
eventually drops it. Hardware implementation of the unit is a simple VLIW processor with
32 single-bit registers (0 - 31). The registers are organized as follows:
- 0: don't touch (always 0)
- 1 - 22: general purpose registers
......@@ -22,54 +22,54 @@
1. CMP offset, value, mask, oper, Rd:
------------------------------------------
* Rd = Rd oper ((((uint16_t *)packet) [offset] & mask) == value)
Examples:
* CMP 3, 0xcafe, 0xffff, MOV, Rd
* CMP 3, 0xcafe, 0xffff, MOV, Rd
will compare the 3rd word of the packet (bytes 6, 7) against 0xcafe and if the words are equal,
1 will be written to Rd register.
* CMP 4, 0xbabe, 0xffff, AND, Rd
will do the same with the 4th word and write to Rd its previous value ANDed with the result
of the comparison. Effectively, Rd now will be 1 only if bytes [6..9] of the payload contain word
0xcafebabe.
Note that the mask value is nibble-granular. That means you can choose a particular
0xcafebabe.
Note that the mask value is nibble-granular. That means you can choose a particular
set of nibbles within a word to be compared, but not an arbitrary set of bits (e.g. 0xf00f, 0xff00
and 0xf0f0 masks are ok, but 0x8001 is wrong.
2. BTST offset, bit_number, oper, Rd
------------------------------------------
* Rd = Rd oper (((uint16_t *)packet) [offset] & (1<<bit_number) ? 1 : 0)
Examples:
* BTST 3, 10, MOV, 11
will write 1 to reg 11 if the 10th bit in the 3rd word of the packet is set (and 0 if it's clear)
3. Logic opearations:
-----------------------------------------
* LOGIC2 Rd, Ra, OPER Rb - 2 argument logic (Rd = Ra OPER Rb). If the operation is MOV or NOT, Ra is
taken as the source register.
* LOGIC3 Rd, Ra, OPER Rb, OPER2, Rc - 3 argument logic Rd = (Ra OPER Rb) OPER2 Rc.
4. Misc
-----------------------------------------
FIN instruction terminates the program.
NOP executes a dummy instruction (LOGIC2 0, 0, AND, 0)
IMPORTANT:
- the program counter is advanved each time a 16-bit words of the packet arrives.
- the program counter is advanved each time a 16-bit words of the packet arrives.
- the CPU doesn't have any interlocks to simplify the HW, so you can't compare the
10th word when PC = 2. Max comparison offset is always equal to the address of the instruction.
- Code may contain up to 64 operations, but it must classify shorter packets faster than in
32 instructions (there's no flow throttling)
*/
#include <stdio.h>
......@@ -79,7 +79,7 @@
#define PFILTER_MAX_CODE_SIZE 32
#define pfilter_dbg
#define pfilter_dbg
extern volatile struct EP_WB *EP;
......@@ -111,19 +111,19 @@ static void check_reg_range(int val, int minval, int maxval, char *name)
pfilter_dbg("microcode: %s register out of range (%d to %d)", name, minval,maxval);
}
}
void pfilter_cmp(int offset, int value, int mask, pfilter_op_t op, int rd)
{
uint64_t ir;
check_size();
if(offset > code_pos)
pfilter_dbg("microcode: comparison offset is bigger than current PC. Insert some nops before comparing");
check_reg_range(rd, 1, 15, "ra/rd");
ir = (PF_MODE_CMP | ((uint64_t)offset << 7)
| ((mask & 0x1) ? (1ULL<<29) : 0)
| ((mask & 0x10) ? (1ULL<<30) : 0)
......@@ -142,19 +142,19 @@ void pfilter_btst(int offset, int bit_index, pfilter_op_t op, int rd)
uint64_t ir;
check_size();
if(offset > code_pos)
pfilter_dbg("microcode: comparison offset is bigger than current PC. Insert some nops before comparing");
check_reg_range(rd, 1, 15, "ra/rd");
check_reg_range(bit_index, 0, 15, "bit index");
ir = ((1ULL<<33) | PF_MODE_CMP | ((uint64_t)offset << 7) | ((uint64_t)bit_index << 29) | (uint64_t)op | ((uint64_t)rd << 3));
code_buf[code_pos++] = ir;
}
void pfilter_nop()
void pfilter_nop()
{
uint64_t ir;
check_size();
......@@ -191,7 +191,7 @@ static void pfilter_logic3(int rd, int ra, pfilter_op_t op, int rb, pfilter_op_t
code_buf[code_pos++] = ir;
}
/* Terminates the microcode, loads it to the endpoint and enables the pfilter */
/* Terminates the microcode, loads it to the endpoint and enables the pfilter */
void pfilter_load()
{
int i;
......@@ -204,11 +204,11 @@ void pfilter_load()
uint32_t cr0, cr1;
cr1 = EP_PFCR1_MM_DATA_LSB_W(code_buf[i] & 0xfff);
cr0 = EP_PFCR0_MM_ADDR_W(i) | EP_PFCR0_MM_DATA_MSB_W(code_buf[i]>>12) | EP_PFCR0_MM_WRITE_MASK;
EP->PFCR1 = cr1;
EP->PFCR0 = cr0;
}
EP->PFCR0 = EP_PFCR0_ENABLE;
}
......@@ -228,34 +228,34 @@ void pfilter_init_default()
pfilter_cmp(0, 0xffff, 0xffff, MOV, 1);
pfilter_cmp(1, 0xffff, 0xffff, AND, 1);
pfilter_cmp(2, 0xffff, 0xffff, AND, 1); /* r1 = 1 when dst mac is broadcast */
pfilter_cmp(0, 0x011b, 0xffff, MOV, 2);
pfilter_cmp(0, 0x011b, 0xffff, MOV, 2);
pfilter_cmp(1, 0x1900, 0xffff, AND, 2);
pfilter_cmp(2, 0x0000, 0xffff, AND, 2); /* r2 = 1 when dst mac is PTP multicast (01:1b:19:00:00:00) */
pfilter_cmp(0, EP->MACH & 0xffff, 0xffff, MOV, 3);
pfilter_cmp(0, EP->MACH & 0xffff, 0xffff, MOV, 3);
pfilter_cmp(1, EP->MACL >> 16, 0xffff, AND, 3);
pfilter_cmp(2, EP->MACL & 0xffff, 0xffff, AND, 3); /* r3 = 1 when the packet is unicast to our own MAC */
pfilter_cmp(6, 0x0800, 0xffff, MOV, 4); /* r4 = 1 when ethertype = IPv4 */
pfilter_cmp(6, 0x0800, 0xffff, MOV, 4); /* r4 = 1 when ethertype = IPv4 */
pfilter_cmp(6, 0x88f7, 0xffff, MOV, 5); /* r5 = 1 when ethertype = PTPv2 */
pfilter_cmp(6, 0x0806, 0xffff, MOV, 6); /* r6 = 1 when ethertype = ARP */
/* Ethernet = 14 bytes, Offset to type in IP: 8 bytes = 22/2 = 11 */
pfilter_cmp(11,0x0001, 0x00ff, MOV, 7); /* r7 = 1 when IP type = ICMP */
pfilter_cmp(11,0x0011, 0x00ff, MOV, 8); /* r8 = 1 when IP type = UDP */
pfilter_logic3(10, 3, OR, 0, AND, 4); /* r10 = IP(unicast) */
pfilter_logic3(11, 1, OR, 3, AND, 4); /* r11 = IP(unicast+broadcast) */
pfilter_logic3(14, 1, AND, 6, OR, 5); /* r14 = ARP(broadcast) or PTPv2 */
pfilter_logic3(15, 10, AND, 7, OR, 14); /* r15 = ICMP/IP(unicast) or ARP(broadcast) or PTPv2 */
/* Ethernet = 14 bytes, IPv4 = 20 bytes, offset to dport: 2 = 36/2 = 18 */
pfilter_cmp(18, 0x0044, 0xffff, MOV, 14); /* r14 = 1 when dport = BOOTPC */
pfilter_logic3(14, 14, AND, 8, AND, 11); /* r14 = BOOTP/UDP/IP(unicast|broadcast) */
pfilter_logic2(15, 14, OR, 15); /* r15 = BOOTP/UDP/IP(unicast|broadcast) or ICMP/IP(unicast) or ARP(broadcast) or PTPv2 */
pfilter_logic3(20, 11, AND, 8, OR, 15); /* r16 = Something we accept */
pfilter_logic2(R_DROP, 20, NOT, 0); /* None match? drop */
pfilter_logic2(R_CLASS(7), 11, AND, 8); /* class 7: UDP/IP(unicast|broadcast) => external fabric */
pfilter_logic2(R_CLASS(0), 15, MOV, 0); /* class 0: ICMP/IP(unicast) or ARP(broadcast) or PTPv2 => PTP LM32 core */
......@@ -278,5 +278,5 @@ void pfilter_init_default()
pfilter_logic2(R_CLASS(0), 6, MOV, 0); /* class 0: PTPv2 => PTP LM32 core */
pfilter_load();
#endif
}
\ No newline at end of file
......@@ -111,14 +111,14 @@ uint8_t mi2c_devprobe(uint8_t i2cif, uint8_t i2c_addr)
//void mi2c_scan(uint8_t i2cif)
//{
// int i;
//
//
// //for(i=0;i<0x80;i++)
// for(i=0x50;i<0x51;i++)
// {
// mi2c_start(i2cif);
// if(!mi2c_put_byte(i2cif, i<<1)) mprintf("found : %x\n", i);
// mi2c_stop(i2cif);
//
// }
//
// }
// mprintf("Nothing more found...\n");
//}
......@@ -42,11 +42,11 @@ static volatile uint32_t dma_tx_buf[MINIC_DMA_TX_BUF_SIZE / 4];
static volatile uint32_t dma_rx_buf[MINIC_DMA_RX_BUF_SIZE / 4];
struct wr_minic {
volatile uint32_t *rx_head, *rx_base;
volatile uint32_t *rx_head, *rx_base;
uint32_t rx_avail, rx_size;
volatile uint32_t *tx_head, *tx_base;
uint32_t tx_avail, tx_size;
int tx_count, rx_count;
};
......@@ -127,14 +127,14 @@ static void minic_new_tx_buffer()
minic.tx_head = minic.tx_base;
minic.tx_avail = minic.tx_size;
minic_writel(MINIC_REG_TX_ADDR, (uint32_t) minic.tx_base);
}
void minic_init()
{
uint32_t lo , hi;
minic_writel(MINIC_REG_EIC_IDR, MINIC_EIC_IDR_RX);
minic_writel(MINIC_REG_EIC_ISR, MINIC_EIC_ISR_RX);
minic.rx_base = dma_rx_buf;
......@@ -143,7 +143,7 @@ void minic_init()
/* FIXME: now we have a temporary HW protection against accidentally overwriting the memory - there's some
very well hidden bug in Minic's RX logic which sometimes causes an overwrite of the memory outside
the buffer. */
lo = (uint32_t)minic.rx_base >> 2;
hi = ((uint32_t)minic.rx_base >> 2) + (sizeof(dma_rx_buf)>>2) - 1;
......@@ -196,16 +196,16 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
//otherwise, weird !!
mprintf("invalid descriptor @%x = %x\n", (uint32_t)minic.rx_head, desc_hdr);
minic_new_rx_buffer();
}
}
return 0;
}
payload_size = RX_DESC_SIZE(desc_hdr);
num_words = ((payload_size + 3) >> 2) + 1;
/* valid packet */
/* valid packet */
if(!RX_DESC_ERROR(desc_hdr))
{
{
if(RX_DESC_HAS_OOB(desc_hdr) && hwts != NULL)
{
......@@ -223,7 +223,7 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
pps_gen_get_time(&sec, &counter_ppsg);
if(counter_r > 3*REF_CLOCK_FREQ_HZ/4 && counter_ppsg < 250000000)
sec--;
sec--;
hwts->sec = sec & 0x7fffffff ;
......@@ -243,8 +243,8 @@ int minic_rx_frame(uint8_t *hdr, uint8_t *payload, uint32_t buf_size, struct hw_
minic_rx_memcpy(hdr, (void*)minic.rx_head + 4, ETH_HEADER_SIZE);
minic_rx_memcpy(payload, (void*)minic.rx_head + 4 + ETH_HEADER_SIZE, n_recvd - ETH_HEADER_SIZE);
}
else {
}
else {
n_recvd = -1;
}
minic_rxbuf_free(num_words);
......@@ -288,7 +288,7 @@ int minic_tx_frame(uint8_t *hdr, uint8_t *payload, uint32_t size, struct hw_time
d_hdr = TX_DESC_WITH_OOB | (WRPC_FID<<12);
d_hdr |= TX_DESC_VALID | nwords;
*(volatile uint32_t *)(minic.tx_head) = d_hdr;
*(volatile uint32_t *)(minic.tx_head + nwords) = 0;
......
......@@ -43,14 +43,14 @@ int8_t get_persistent_mac(uint8_t portnum, uint8_t* mac)
uint8_t read_buffer[32];
uint8_t i;
int8_t out;
out = -1;
if(devsnum == 0) return out;
for (i = 0; i < devsnum; ++i) {
//#if DEBUG_PMAC
mprintf("Found device: %x:%x:%x:%x:%x:%x:%x:%x\n",
mprintf("Found device: %x:%x:%x:%x:%x:%x:%x:%x\n",
FamilySN[i][7], FamilySN[i][6], FamilySN[i][5], FamilySN[i][4],
FamilySN[i][3], FamilySN[i][2], FamilySN[i][1], FamilySN[i][0]);
//#endif
......@@ -65,7 +65,7 @@ int8_t get_persistent_mac(uint8_t portnum, uint8_t* mac)
mprintf("Using temperature ID for MAC\n");
#endif
}
/* If there is an EEPROM, read page 0 for the MAC */
if (FamilySN[i][0] == 0x43) {
owLevel(portnum, MODE_NORMAL);
......@@ -79,14 +79,14 @@ int8_t get_persistent_mac(uint8_t portnum, uint8_t* mac)
memcpy(mac, read_buffer, 6);
out = 0;
#if DEBUG_PMAC
mprintf("Using EEPROM page: %x:%x:%x:%x:%x:%x\n",
mprintf("Using EEPROM page: %x:%x:%x:%x:%x:%x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
#endif
}
}
}
}
return out;
}
......@@ -98,18 +98,18 @@ int8_t set_persistent_mac(uint8_t portnum, uint8_t* mac)
// Find the device (only the first one, we won't write MAC to all EEPROMs out there, right?)
if( FindDevices(portnum, &FamilySN[0], 0x43, 1) == 0) return -1;
memset(write_buffer, 0, sizeof(write_buffer));
memcpy(write_buffer, mac, 6);
#if DEBUG_PMAC
mprintf("Writing to EEPROM\n");
#endif
/* Write the last EEPROM with the MAC */
owLevel(portnum, MODE_NORMAL);
if (Write43(portnum, FamilySN[0], EEPROM_MAC_PAGE, &write_buffer) == TRUE)
return 0;
return -1;
}
......@@ -40,7 +40,7 @@ int pps_gen_adjust(int counter, int64_t how_much)
{
uint32_t cr;
TRACE_DEV("Adjust: counter = %s [%c%d]\n",
TRACE_DEV("Adjust: counter = %s [%c%d]\n",
counter == PPSG_ADJUST_SEC ? "seconds" : "nanoseconds", how_much<0?'-':'+', (int32_t)abs(how_much));
if(counter == PPSG_ADJUST_NSEC)
......@@ -75,12 +75,12 @@ uint64_t pps_get_utc(void)
{
uint64_t out;
uint32_t low, high;
low = ppsg_read(CNTR_UTCLO);
high = ppsg_read(CNTR_UTCHI);
high &= 0xFF; /* CNTR_UTCHI has only 8 bits defined -- rest are HDL don't care */