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Software for White Rabbit PTP Core
Commit 2a2a8dfb authored by Peter Jansweijer's avatar Peter Jansweijer
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Settings for (deprecated) Morion MV137 on 100MHzInTheLoop v1

parent b7682436
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    Showing with 16 additions and 13 deletions
    boards/spec7/board.c
    View file @ 2a2a8dfb
    ......@@ -88,17 +88,17 @@ int implement_two_stages = 1; // implement 2-stage ocxo lock later
    /* configure a suitable PI gain schedule for the SoftPLL: */
    spll_gain_schedule_t* gs= &spll_main_ocxo_gain_sched;
    /* we start with the default values (Bandwidth 100 Hz) */
    gs->stages[0].kp = -4000;
    gs->stages[0].ki = -100;
    gs->stages[0].lock_samples = 10000;
    /* we start with the default values (bandwisth ~100 Hz, Lock reasonably fast) */
    gs->stages[0].kp = -5500;
    gs->stages[0].ki = -30;
    gs->stages[0].lock_samples = 30000;
    gs->stages[0].shift = 12;
    /* once it's locked, the loop bandwidth is switched to 15 Hz to filter out WR link added phase noise */
    gs->stages[1].kp = -600;
    gs->stages[1].ki = -2;
    /* once it's locked, the loop bandwidth is switched to 2.5 Hz to filter out WR link added phase noise */
    gs->stages[1].kp = -3000;
    gs->stages[1].ki = -5;
    gs->stages[1].lock_samples = 10000;
    gs->stages[1].shift = 12;
    gs->stages[1].shift = 16;
    if ( implement_two_stages ) {
    gs->n_stages = 2; // 2 stages: OCXO
    ......
    boards/spec7/board.h
    View file @ 2a2a8dfb
    ......@@ -30,9 +30,9 @@
    #define REF_CLOCK_PERIOD_PS 16000
    #define REF_CLOCK_FREQ_HZ 62500000
    /* Accomodate 20 bit MAX5719A */
    #define BOARD_SPLL_DAC_BITS 20
    #define BOARD_SPLL_DIV_BITS 4
    /* 100MHzInTheLoop V1 (Morion MV137) is based on 16 bit DAC LTC2641 */
    #define BOARD_SPLL_DAC_BITS 16
    #define BOARD_SPLL_DIV_BITS 0
    /* Maximum number of simultaneously created sockets */
    #define NET_MAX_SOCKETS 12
    ......
    ppsi @ b1457bc6
    Subproject commit 49833dde2fcbed69df4191cb4901d1f533e0e009
    Subproject commit b1457bc6f6721f28df0fcd004d6b6327105eb0f9
    softpll/spll_helper.c
    View file @ 2a2a8dfb
    ......@@ -16,9 +16,12 @@ void helper_very_init( struct spll_helper_state *s )
    /* Phase branch PI controller */
    s->pi.y_min = (5 << BOARD_SPLL_DIV_BITS);
    s->pi.y_max = (1 << BOARD_SPLL_DAC_BITS) - (5 << BOARD_SPLL_DIV_BITS);
    #if defined(CONFIG_WR_NODE)
    #if defined(CONFIG_WR_NODE) && !defined(CONFIG_TARGET_SPEC7)
    s->pi.kp = -150;
    s->pi.ki = -2;
    #elif defined(CONFIG_WR_NODE) && defined(CONFIG_TARGET_SPEC7)
    s->pi.kp = -750;
    s->pi.ki = -2;
    #else
    s->pi.kp = 150;
    s->pi.ki = 2;
    ......
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