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Software for White Rabbit PTP Core
Commit 417f1e9d authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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doc: remove old HDL figures

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doc/HDLdoc/fabric.tex
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\subsubsection{Fabric interface} \subsubsection{Fabric interface}
\label{sec:wrpc_fabric} \label{sec:wrpc_fabric}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=\textwidth]{fig/wrpc_fabric.pdf}
% \caption{WR Fabric interface}
% \end{center}
%\end{figure}
The Fabric interface is used for sending and receiving Ethernet frames. It consists The Fabric interface is used for sending and receiving Ethernet frames. It consists
of two pipelined Wishbone interfaces operating independently: of two pipelined Wishbone interfaces operating independently:
......
doc/HDLdoc/periph.tex
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\subsubsection{GPIO/UART/I2C/1-Wire/SPI interfaces} \subsubsection{GPIO/UART/I2C/1-Wire/SPI interfaces}
\label{sec:wrpc_periph} \label{sec:wrpc_periph}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.9\textwidth]{fig/basic_wrpc_gpio.pdf}
% \caption{Other interfaces of WRPC}
% \end{center}
%\end{figure}
Several hardware peripherals can be connected to the White Rabbit PTP Core. It Several hardware peripherals can be connected to the White Rabbit PTP Core. It
has: has:
\begin{itemize} \begin{itemize}
......
doc/HDLdoc/phyif.tex
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\subsubsection{PHY interface} \subsubsection{PHY interface}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.7\textwidth]{fig/wrpc_phyif.pdf}
% \caption{PHY interface of WRPC}
% \end{center}
%\end{figure}
The interface connects WRPC with the Ethernet PHY layer IP-core. The interface is generic, but The interface connects WRPC with the Ethernet PHY layer IP-core. The interface is generic, but
currently three Gigabit Ethernet PHYs are tested and supported: currently three Gigabit Ethernet PHYs are tested and supported:
......
doc/HDLdoc/timecode.tex
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\subsubsection{Timecode interface} \subsubsection{Timecode interface}
\label{sec:wrpc_timecode} \label{sec:wrpc_timecode}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.5\textwidth]{fig/basic_wrpc_tm.pdf}
% \caption{Timecode output interface of WRPC}
% \end{center}
%\end{figure}
Timecode interface provides current time to the other HDL modules in a form that Timecode interface provides current time to the other HDL modules in a form that
can be easily used. It consists of: a 1-PPS and a UTC timecode can be easily used. It consists of: a 1-PPS and a UTC timecode
aligned to the time of WR Master. aligned to the time of WR Master.
......
doc/HDLdoc/txts.tex
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\subsubsection{Tx Timestamping interface} \subsubsection{Tx Timestamping interface}
\label{sec:txts} \label{sec:txts}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.4\textwidth]{fig/wrpc_txts.pdf}
% \caption{Tx timestamping interface of WRPC}
% \end{center}
%\end{figure}
The Tx Timestamping interface provides the timestamps generated inside WRPC for each The Tx Timestamping interface provides the timestamps generated inside WRPC for each
Ethernet frame transmitted from user-defined module through the WRF Sink interface.\\ Ethernet frame transmitted from user-defined module through the WRF Sink interface.\\
doc/HDLdoc/wb.tex
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\subsubsection{External Wishbone Slave/Master interface} \subsubsection{External Wishbone Slave/Master interface}
\label{sec:wrpc_wb} \label{sec:wrpc_wb}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.7\textwidth]{fig/wrpc_wb.pdf}
% \caption{External Wishbone interfaces of WRPC}
% \end{center}
%\end{figure}
{\bf Ext WB Slave} is a Wishbone slave interface (see the Wishbone bus specification~\cite{wb_spec} {\bf Ext WB Slave} is a Wishbone slave interface (see the Wishbone bus specification~\cite{wb_spec}
for more details). It controls the primary Wishbone Crossbar insisde the WRPC and thus provides for more details). It controls the primary Wishbone Crossbar insisde the WRPC and thus provides
access to all the WRPC internals. access to all the WRPC internals.
......
doc/HDLdoc/wrc_ports.tex
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\subsubsection{Ports} \subsubsection{Ports}
\label{sec:wrc_ports} \label{sec:wrc_ports}
%\begin{figure}[ht]
% \begin{center}
% \includegraphics[width=.8\textwidth]{fig/basic_wrpc_clk.pdf}
% \caption{Mandatory clock signals and main reset of WRPC}
% \end{center}
%\end{figure}
\begin{hdlporttable} \begin{hdlporttable}
\hdltablesection{Clocks and resets}\\ \hdltablesection{Clocks and resets}\\
\hline \hline
......
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