include/hw: added missing IUART registers header

62b748a1 · Tomasz Wlostowski · c4b36f99 · 62b748a1
Commit 62b748a1 authored Sep 25, 2019 by Tomasz Wlostowski
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wb_insn_uart.h include/hw/wb_insn_uart.h +132 -0

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--- a/include/hw/wb_insn_uart.h
+++ b/include/hw/wb_insn_uart.h
+/*
+  Register definitions for slave core: INSN UART
+
+  * File           : wb_insn_uart.h
+  * Author         : auto-generated by wbgen2 from insn_uart_wb.wb
+  * Created        : Mon Jul 22 17:02:40 2019
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE insn_uart_wb.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_INSN_UART_WB_WB
+#define __WBGEN2_REGDEFS_INSN_UART_WB_WB
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <inttypes.h>
+#endif
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Status */
+
+/* definitions for field: Tx Busy in reg: Status */
+#define IUART_SR_TXBSY                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Rx Ready in reg: Status */
+#define IUART_SR_RXRDY                        WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Rx Overflow or dropped char in reg: Status */
+#define IUART_SR_RXERR                        WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: GP Ctrl lines in reg: Status */
+#define IUART_SR_GP_CTRL_MASK                 WBGEN2_GEN_MASK(3, 8)
+#define IUART_SR_GP_CTRL_SHIFT                3
+#define IUART_SR_GP_CTRL_W(value)             WBGEN2_GEN_WRITE(value, 3, 8)
+#define IUART_SR_GP_CTRL_R(reg)               WBGEN2_GEN_READ(reg, 3, 8)
+
+/* definitions for field: Tx data valid in reg: Status */
+#define IUART_SR_TXDATA_VALID                 WBGEN2_GEN_MASK(11, 1)
+
+/* definitions for field: CPL data valid in reg: Status */
+#define IUART_SR_CPLS_VALID                   WBGEN2_GEN_MASK(12, 1)
+
+/* definitions for field: unused in reg: Status */
+#define IUART_SR_UNUSED_MASK                  WBGEN2_GEN_MASK(13, 19)
+#define IUART_SR_UNUSED_SHIFT                 13
+#define IUART_SR_UNUSED_W(value)              WBGEN2_GEN_WRITE(value, 13, 19)
+#define IUART_SR_UNUSED_R(reg)                WBGEN2_GEN_READ(reg, 13, 19)
+
+/* definitions for register: Fifo counters */
+
+/* definitions for field: txfifo cnt in reg: Fifo counters */
+#define IUART_FIFO_TXCNT_MASK                 WBGEN2_GEN_MASK(0, 16)
+#define IUART_FIFO_TXCNT_SHIFT                0
+#define IUART_FIFO_TXCNT_W(value)             WBGEN2_GEN_WRITE(value, 0, 16)
+#define IUART_FIFO_TXCNT_R(reg)               WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: rxfifo cnt in reg: Fifo counters */
+#define IUART_FIFO_RXCNT_MASK                 WBGEN2_GEN_MASK(16, 16)
+#define IUART_FIFO_RXCNT_SHIFT                16
+#define IUART_FIFO_RXCNT_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
+#define IUART_FIFO_RXCNT_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: uart access enable */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for register: RX overflow or dropped char */
+
+/* definitions for register: Escape Character */
+
+/* definitions for register: Start Insn */
+
+/* definitions for register: Start Write */
+
+/* definitions for register: Start Read */
+
+/* definitions for register: Start Cpl */
+
+/* definitions for register: END */
+
+/* definitions for register: Start Ctrl */
+
+/* definitions for register: Stop Ctrl */
+/* [0x0]: REG Status */
+#define IUART_REG_SR 0x00000000
+/* [0x4]: REG Fifo counters */
+#define IUART_REG_FIFO 0x00000004
+/* [0x8]: REG uart access enable */
+#define IUART_REG_UART_EN 0x00000008
+/* [0xc]: REG Transmit data regsiter */
+#define IUART_REG_TX_FIFO_DATA 0x0000000c
+/* [0x10]: REG Receive data regsiter */
+#define IUART_REG_RX_FIFO_DATA 0x00000010
+/* [0x14]: REG RX overflow or dropped char */
+#define IUART_REG_RX_DROPPED 0x00000014
+/* [0x18]: REG Escape Character */
+#define IUART_REG_ESC_CHAR 0x00000018
+/* [0x1c]: REG Start Insn */
+#define IUART_REG_START_INSN_CHAR 0x0000001c
+/* [0x20]: REG Start Write */
+#define IUART_REG_START_WRITE_CHAR 0x00000020
+/* [0x24]: REG Start Read */
+#define IUART_REG_START_READ_CHAR 0x00000024
+/* [0x28]: REG Start Cpl */
+#define IUART_REG_START_CPL_CHAR 0x00000028
+/* [0x2c]: REG END */
+#define IUART_REG_END_CHAR 0x0000002c
+/* [0x30]: REG Start Ctrl */
+#define IUART_REG_WRITE_CTRL_CHAR 0x00000030
+/* [0x34]: REG Stop Ctrl */
+#define IUART_REG_READ_CTRL_CHAR 0x00000034
+#endif