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Software for White Rabbit PTP Core
Commit 6d5af797 authored by Alessandro Rubini's avatar Alessandro Rubini
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softpll-unify: spll_defs differ between wrc and wrs 

Signed-off-by: Alessandro Rubini's avatarAlessandro Rubini <rubini@gnudd.com>
parent 901dae16
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Showing with 21 additions and 11 deletions
include/board-wrc.h
View file @ 6d5af797
...@@ -31,4 +31,11 @@ ...@@ -31,4 +31,11 @@
int board_init(); int board_init();
int board_update(); int board_update();
/* spll parameter that are board-specific */
#define BOARD_DIVIDE_DMTD_CLOCKS 1
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#endif /* __BOARD_WRC_H */ #endif /* __BOARD_WRC_H */
include/board-wrs.h
View file @ 6d5af797
...@@ -3,8 +3,9 @@ ...@@ -3,8 +3,9 @@
/* RT CPU Memory layout */ /* RT CPU Memory layout */
#define CPU_CLOCK 62500000 #define CPU_CLOCK 62500000
#define REF_CLOCK_PERIOD_PS 16000 #define REF_CLOCK_FREQ_HZ 62500000
#define REF_CLOCK_PERIOD_PS 16000
#define UART_BAUDRATE 115200 #define UART_BAUDRATE 115200
...@@ -15,4 +16,10 @@ ...@@ -15,4 +16,10 @@
#define BASE_TIMER 0x10400 #define BASE_TIMER 0x10400
#define BASE_PPS_GEN 0x10500 #define BASE_PPS_GEN 0x10500
/* spll parameter that are board-specific */
#define BOARD_DIVIDE_DMTD_CLOCKS 0
#define BOARD_MAX_CHAN_REF 18
#define BOARD_MAX_CHAN_AUX 1
#define BOARD_MAX_PTRACKERS 18
#endif #endif
include/spll_defs.h
View file @ 6d5af797
...@@ -18,8 +18,8 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia ...@@ -18,8 +18,8 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
/* optional DMTD clock division to improve FPGA timing closure by avoiding /* optional DMTD clock division to improve FPGA timing closure by avoiding
clock nets directly driving FD inputs. Must be consistent with the clock nets directly driving FD inputs. Must be consistent with the
g_divide_inputs_by_2 generic. */ g_divide_inputs_by_2 generic. This is different in wrs and wrc */
#define DIVIDE_DMTD_CLOCKS_BY_2 1 #define DIVIDE_DMTD_CLOCKS_BY_2 BOARD_DIVIDE_DMTD_CLOCKS
/* Number of bits in phase tags generated by the DMTDs. Used to sign-extend the tags. /* Number of bits in phase tags generated by the DMTDs. Used to sign-extend the tags.
Corresponding VHDL generic: g_tag_bits. */ Corresponding VHDL generic: g_tag_bits. */
...@@ -34,13 +34,13 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia ...@@ -34,13 +34,13 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
#define PI_FRACBITS 12 #define PI_FRACBITS 12
/* Max. allowed number of reference channels. Can be used to tweak memory usage. */ /* Max. allowed number of reference channels. Can be used to tweak memory usage. */
#define MAX_CHAN_REF 1 #define MAX_CHAN_REF BOARD_MAX_CHAN_REF /* Depends on wrc/wrs */
/* Max. allowed number of auxillary channels */ /* Max. allowed number of auxillary channels */
#define MAX_CHAN_AUX 2 #define MAX_CHAN_AUX BOARD_MAX_CHAN_AUX /* Depends on wrc/wrs */
/* Max. allowed number of phase trackers */ /* Max. allowed number of phase trackers */
#define MAX_PTRACKERS 1 #define MAX_PTRACKERS BOARD_MAX_PTRACKERS /* Depends on wrc/wrs */
/* Number of bits of the DAC(s) driving the oscillator(s). Must be the same for /* Number of bits of the DAC(s) driving the oscillator(s). Must be the same for
all the outputs. */ all the outputs. */
...@@ -48,7 +48,3 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia ...@@ -48,7 +48,3 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
/* Number of samples in a single ptracker averaging bin */ /* Number of samples in a single ptracker averaging bin */
#define PTRACKER_AVERAGE_SAMPLES 512 #define PTRACKER_AVERAGE_SAMPLES 512
/* 1.0 / (Speed of the phase shifter) - the higher value, the slower phase shifting.
Used to prevent de-locking PLLs when shifting large offsets. */
#define PHASE_SHIFTER_SPEED 1
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