Commit bc837873 authored by Peter Jansweijer's avatar Peter Jansweijer

make wr_s_lock_timeout board dependent

parent 5c71272b
Pipeline #5077 failed with stage
in 2 minutes and 23 seconds
......@@ -34,6 +34,10 @@
#define BOARD_SPLL_DAC_BITS 20
#define BOARD_SPLL_DIV_BITS 4
/* When using an external oscillator,
it can take more than 15sec to sync PLL */
#define BOARD_WR_S_LOCK_TIMEOUT_MS 30000
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
......
Subproject commit 49833dde2fcbed69df4191cb4901d1f533e0e009
Subproject commit a986e0fde03eb33c9821a3e746db833c0af194f7
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