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Software for White Rabbit PTP Core
Commit c2f36004 authored by Peter Jansweijer's avatar Peter Jansweijer
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set Kp, Ki for KVG ocxo

parent d66153d3
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    boards/babywr/board.c
    View file @ c2f36004
    ......@@ -272,22 +272,22 @@ void gpio_control_init()
    static void babywr_spll_setup(void)
    {
    int implement_two_stages = 0; // implement 2-stage ocxo lock later
    int implement_two_stages = 1; // implement 2-stage ocxo lock later
    /* configure a suitable PI gain schedule for the SoftPLL: */
    spll_gain_schedule_t* gs= &spll_main_ocxo_gain_sched;
    /* we start with the default SiT5359 values (Bandwidth ~20 Hz) */
    gs->stages[0].kp = -1800; // use 1400 when X1 = 125 MHz
    gs->stages[0].ki = -25;
    gs->stages[0].kp = -4000; // use 1400 when X1 = 125 MHz
    gs->stages[0].ki = -8;
    gs->stages[0].lock_samples = 10000;
    gs->stages[0].shift = 12;
    /* once it's locked, the loop bandwidth is switched to low bandwidth to filter out WR link added phase noise */
    gs->stages[1].kp = -3000;
    gs->stages[1].ki = -5;
    gs->stages[1].kp = -600;
    gs->stages[1].ki = -2;
    gs->stages[1].lock_samples = 10000;
    gs->stages[1].shift = 16;
    gs->stages[1].shift = 12;
    if ( implement_two_stages ) {
    gs->n_stages = 2; // 2 stages: OCXO
    ......
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