doc: add aux clk interface

c527b49c · Grzegorz Daniluk · 417f1e9d · c527b49c · 417f1e9d · 417f1e9d
Commit c527b49c authored Mar 13, 2017 by Grzegorz Daniluk
5 changed files
--- a/doc/HDLdoc/aux_clocks.tex
+++ b/doc/HDLdoc/aux_clocks.tex
 \subsubsection{Aux clocks}

-\begin{figure}[ht]
-  \begin{center}
-    \includegraphics[width=.8\textwidth]{fig/adv_wrpc_clk.pdf}
-    \caption{Aux clock synchronization interface}
-  \end{center}
-\end{figure}
-
 The WRPC can syntonize auxiliary clock signals to the White Rabbit timebase. It
 is done with a similar PLL that is used to discipline the local reference clock
 (section \ref{basic:clk_rst}). WRPC provides tuning values for the VCXO producing
 clock signal which is connected to \emph{clk\_aux\_i}.
-
-\begin{hdlporttable}
-\end{hdlporttable}
--- a/doc/HDLdoc/fig/adv_wrpc_clk.pdf
+++ b/doc/HDLdoc/fig/adv_wrpc_clk.pdf
--- a/doc/HDLdoc/fig/wrpc_tsys.pdf
+++ b/doc/HDLdoc/fig/wrpc_tsys.pdf
--- a/doc/HDLdoc/timing.tex
+++ b/doc/HDLdoc/timing.tex
-\section{Timing system}
-\label{sec:tim_sys}
-
-\begin{figure}[ht]
-  \begin{center}
-    \includegraphics[width=.8\textwidth]{fig/wrpc_tsys.pdf}
-  \end{center}
-\end{figure}
-
-Timing system outputs are mandatory part of WRPC PLLs that discipline local
-oscillators.
-
-\begin{center}
-  \begin{tabular}{|l|l|p{11cm}|}
-    \hline {\bf name} & {\bf size} & {\bf description} \\
-    \hline
-    \emph{dac\_hpll\_load\_p1\_o} & 1 & validates DAC value on data port \\
-    \emph{dac\_hpll\_data\_o} & 16 & DAC value for tuning helper (DMTD) VCXO\\
-    \hline
-    \emph{dac\_dpll\_load\_p1\_o} & 1 & validates DAC value on data port \\
-    \emph{dac\_dpll\_data\_o} & 16 & DAC value for tuning main (ref) VCXO\\
-    \hline
-  \end{tabular}
-\end{center}
--- a/doc/HDLdoc/wrc_core.tex
+++ b/doc/HDLdoc/wrc_core.tex
@@ -38,5 +38,6 @@ Section~\ref{sec:hdl_board_spec}).
 \input{HDLdoc/wb.tex}
 \input{HDLdoc/fabric.tex}
 \input{HDLdoc/txts.tex}
+\input{HDLdoc/aux_clocks.tex}
 \input{HDLdoc/timecode.tex}
 \input{HDLdoc/aux_diag.tex}