Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
Software for White Rabbit PTP Core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
32
Issues
32
List
Board
Labels
Milestones
Merge Requests
6
Merge Requests
6
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Software for White Rabbit PTP Core
Commits
c527b49c
Commit
c527b49c
authored
Mar 13, 2017
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
doc: add aux clk interface
parent
417f1e9d
Show whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
1 addition
and
34 deletions
+1
-34
aux_clocks.tex
doc/HDLdoc/aux_clocks.tex
+0
-10
adv_wrpc_clk.pdf
doc/HDLdoc/fig/adv_wrpc_clk.pdf
+0
-0
wrpc_tsys.pdf
doc/HDLdoc/fig/wrpc_tsys.pdf
+0
-0
timing.tex
doc/HDLdoc/timing.tex
+0
-24
wrc_core.tex
doc/HDLdoc/wrc_core.tex
+1
-0
No files found.
doc/HDLdoc/aux_clocks.tex
View file @
c527b49c
\subsubsection
{
Aux clocks
}
\begin{figure}
[ht]
\begin{center}
\includegraphics
[width=.8\textwidth]
{
fig/adv
_
wrpc
_
clk.pdf
}
\caption
{
Aux clock synchronization interface
}
\end{center}
\end{figure}
The WRPC can syntonize auxiliary clock signals to the White Rabbit timebase. It
is done with a similar PLL that is used to discipline the local reference clock
(section
\ref
{
basic:clk
_
rst
}
). WRPC provides tuning values for the VCXO producing
clock signal which is connected to
\emph
{
clk
\_
aux
\_
i
}
.
\begin{hdlporttable}
\end{hdlporttable}
doc/HDLdoc/fig/adv_wrpc_clk.pdf
deleted
100755 → 0
View file @
417f1e9d
File deleted
doc/HDLdoc/fig/wrpc_tsys.pdf
deleted
100755 → 0
View file @
417f1e9d
File deleted
doc/HDLdoc/timing.tex
deleted
100644 → 0
View file @
417f1e9d
\section
{
Timing system
}
\label
{
sec:tim
_
sys
}
\begin{figure}
[ht]
\begin{center}
\includegraphics
[width=.8\textwidth]
{
fig/wrpc
_
tsys.pdf
}
\end{center}
\end{figure}
Timing system outputs are mandatory part of WRPC PLLs that discipline local
oscillators.
\begin{center}
\begin{tabular}
{
|l|l|p
{
11cm
}
|
}
\hline
{
\bf
name
}
&
{
\bf
size
}
&
{
\bf
description
}
\\
\hline
\emph
{
dac
\_
hpll
\_
load
\_
p1
\_
o
}
&
1
&
validates DAC value on data port
\\
\emph
{
dac
\_
hpll
\_
data
\_
o
}
&
16
&
DAC value for tuning helper (DMTD) VCXO
\\
\hline
\emph
{
dac
\_
dpll
\_
load
\_
p1
\_
o
}
&
1
&
validates DAC value on data port
\\
\emph
{
dac
\_
dpll
\_
data
\_
o
}
&
16
&
DAC value for tuning main (ref) VCXO
\\
\hline
\end{tabular}
\end{center}
doc/HDLdoc/wrc_core.tex
View file @
c527b49c
...
...
@@ -38,5 +38,6 @@ Section~\ref{sec:hdl_board_spec}).
\input
{
HDLdoc/wb.tex
}
\input
{
HDLdoc/fabric.tex
}
\input
{
HDLdoc/txts.tex
}
\input
{
HDLdoc/aux
_
clocks.tex
}
\input
{
HDLdoc/timecode.tex
}
\input
{
HDLdoc/aux
_
diag.tex
}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment