Conditional wait on ad9516 lock (for 10->125) or timer_delay (for 125-> 125)

Set bit for Synchronous Reset R, A and B counters on SYNC_n pin

Conditional wait on ad9516 lock (for 10->125) or timer_delay (for 125-> 125)
Set bit for Synchronous Reset R, A and B counters on SYNC_n pin
ee45de9b · Peter Jansweijer · 49b65568 · ee45de9b · ee45de9b
Commit ee45de9b authored Dec 06, 2019 by Peter Jansweijer
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Showing with 4 additions and 2 deletions

ad9516.c dev/ad9516.c +3 -1

ad9516_config.h dev/ad9516_config.h +1 -1

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--- a/dev/ad9516.c
+++ b/dev/ad9516.c
@@ -248,12 +248,14 @@ int spec7_ad9516_init(int ext_10mhz)
  if (ext_10mhz) {
    /* Configuration for the SPEC7: External 10 MHZ In (Bulls-Eye B03/B04) => 125 MHz on outputs 0, 1, 2 */
    ad9516_load_regset(spi_base, ad9516_10mhz_base_config_spec7, ARRAY_SIZE(ad9516_10mhz_base_config_spec7), 0);
+    ad9516_wait_lock(spi_base);
+    pp_printf("AD9516 locked.\n");
  } else {
    /* Configuration for the SPEC7: Forward 125 MHz VCXO_REFCLK at CLK input to outputs 0, 1, 2 */
    ad9516_load_regset(spi_base, ad9516_base_config_spec7, ARRAY_SIZE(ad9516_base_config_spec7), 0);
+    timer_delay(10);    
  }

-	timer_delay(10);
  pp_printf("Switch clk_sys source from free running clk_dmtd to AD9516 output.\n");
 	/* AD9516 now initialized so switch clk_sys from free running clk_dmtd to AD9516 output */
 	gpio_out(GPIO_PLL_CLK_SEL, 1);

--- a/dev/ad9516_config.h
+++ b/dev/ad9516_config.h
@@ -307,7 +307,7 @@ const struct ad9516_reg ad9516_10mhz_base_config_spec7[] = {
 {0x0016, 0x05}, /* DM divide by 16 (16/17 mode) */
 {0x0017, 0x00},
 {0x0018, 0x07},
-{0x0019, 0x00},
+{0x0019, 0x80}, /* Synchronous Reset R, A and B counters on SYNC_n pin */
 {0x001A, 0x00},
 {0x001B, 0x00},
 {0x001C, 0x01}, /* differential reference */