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Software for White Rabbit PTP Core
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f24ed697
Commit
f24ed697
authored
Jan 05, 2023
by
Tristan Gingold
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Makefile
doc/Makefile
+2
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wrpc.tex
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+19
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doc/Makefile
View file @
f24ed697
...
@@ -7,7 +7,9 @@ all : wrpc.pdf
...
@@ -7,7 +7,9 @@ all : wrpc.pdf
.PHONY
:
all clean
.PHONY
:
all clean
wrpc.pdf
:
wrpc.tex HDLdoc/*.tex
wrpc.pdf
:
wrpc.tex HDLdoc/*.tex
# Generate version
bash
-c
"echo '\\newcommand{\\gitrevinfo}{'$(subst _,\\\\_,$(RELEASE))'}' > version.tex"
bash
-c
"echo '\\newcommand{\\gitrevinfo}{'$(subst _,\\\\_,$(RELEASE))'}' > version.tex"
# Run twice to create TOC.
pdflatex
-dPDFSETTINGS
=
/prepress
-dSubsetFonts
=
true
-dEmbedAllFonts
=
true
-dMaxSubsetPct
=
100
-dCompatibilityLevel
=
1.4
$^
pdflatex
-dPDFSETTINGS
=
/prepress
-dSubsetFonts
=
true
-dEmbedAllFonts
=
true
-dMaxSubsetPct
=
100
-dCompatibilityLevel
=
1.4
$^
pdflatex
-dPDFSETTINGS
=
/prepress
-dSubsetFonts
=
true
-dEmbedAllFonts
=
true
-dMaxSubsetPct
=
100
-dCompatibilityLevel
=
1.4
$^
pdflatex
-dPDFSETTINGS
=
/prepress
-dSubsetFonts
=
true
-dEmbedAllFonts
=
true
-dMaxSubsetPct
=
100
-dCompatibilityLevel
=
1.4
$^
...
...
doc/wrpc.tex
View file @
f24ed697
...
@@ -159,8 +159,9 @@ distributed in the following places:
...
@@ -159,8 +159,9 @@ distributed in the following places:
\item
\url
{
https://ohwr.org/project/wrpc-sw.git
}
\item
\url
{
https://ohwr.org/project/wrpc-sw.git
}
Repository with the software running inside the WRPC. As today both, the LM32
Repository with the software running inside the WRPC. Starting from
and the RISC-V soft-core processors are supported by software.
version 5, the soft CPU core is a RISC-V, while previous versions were
using LM32.
\end{itemize*}
\end{itemize*}
Other tools useful for building and running the WRPC can be downloaded from the
Other tools useful for building and running the WRPC can be downloaded from the
...
@@ -173,26 +174,11 @@ following locations:
...
@@ -173,26 +174,11 @@ following locations:
\textit
{
hdlmake
}
is used in the HDL synthesis process to create a Makefile and
\textit
{
hdlmake
}
is used in the HDL synthesis process to create a Makefile and
Xilinx ISE / Altera Quartus project file
Xilinx ISE / Altera Quartus project file
\item
{
\small\url
{
https://ohwr.org/project/wrpc-sw/
uploads/a2e8eeba448fbc8d580e68004e6f6c7f/lm32.tar.x
z
}}
\item
{
\small\url
{
https://ohwr.org/project/wrpc-sw/
wikis/uploads/9f9224d2249848ed3e854636de9c08dc/riscv-11.2-small.tg
z
}}
When the LM32 is used as soft-core processor inside the WRPC, this toolchain
This toolchain based on GCC 11.2 can be used to compile the software
can be used to compile the software for WRPC. This version of the toolchain
for WRPC. This toolchain can work only on 64bit host machines. The
is for 32-bit systems. It can be used on 64-bit systems, but can fail to work
instruction how to build the toolchain for RISC-V can be found in
on some filesystems. If you encounter problems running this toolchain on
modern 64bit machines, try the 64-bit version described below.
\item
{
\small\url
{
https://ohwr.org/project/wrpc-sw/uploads/2776ce0ba43503d1486ae205b48fb450/lm32
_
host
_
64bit.tar.xz
}}
When the LM32 is used as soft-core processor inside the WRPC, this toolchain
can be used to compile the software for WRPC. This is a 64-bit version of
the toolchain. For LM32 architecture this should be the default choice.
\item
{
\small\url
{
https://ohwr.org/project/wrpc-sw/wikis/uploads/e445916c27cc49cc62a370aded9cacb2/riscv
_
gcc
_
11
_
1
_
0.tar.xz
}}
When the RISC-V is used as soft-core processor inside the WRPC, this toolchain
based on GCC 11.0.0 can be used to compile the software for WRPC. This
toolchain can work only on 64bit host machines. The instruction how to build
the toolchain for RISC-V can be found in
the appendix~
\ref
{
appendix:building
_
RISCV
_
toolchain
}
.
the appendix~
\ref
{
appendix:building
_
RISCV
_
toolchain
}
.
\end{itemize*}
\end{itemize*}
...
@@ -251,22 +237,6 @@ the soft-core processor's software, please check also
...
@@ -251,22 +237,6 @@ the soft-core processor's software, please check also
section~
\ref
{
Software compilation
}
section~
\ref
{
Software compilation
}
which contains a description of the software compilation process.
which contains a description of the software compilation process.
% ==========================================================================
\subsection
{
Supported soft-core processors
}
\label
{
Supported soft-core processors
}
% TODO: fix before the release
The release v5.0 of WRPC supports the build with LM32 or RISC-V soft-core
processor. Both, the gateware and software have to be build for the same,
selected architecture.
The main reasons to introduce the RISC-V architecture are:
\begin{itemize}
\item
lack of LM32 support by modern versions of GNU GCC
\item
reduced footprint size of the software
\item
licensing issues
\end{itemize}
% ==========================================================================
% ==========================================================================
\subsection
{
HDL synthesis
}
\subsection
{
HDL synthesis
}
\label
{
HDL synthesis
}
\label
{
HDL synthesis
}
...
@@ -336,13 +306,13 @@ $ chmod a+x /usr/bin/hdlmake
...
@@ -336,13 +306,13 @@ $ chmod a+x /usr/bin/hdlmake
\end
{
lstlisting
}
\end
{
lstlisting
}
Having all the tools in place, you can now clone the main WR PTP Core git
Having all the tools in place, you can now clone the main WR PTP Core git
repository for the v
4
.
1
release. The set of commands below clones the WR PTP Core
repository for the v
5
release. The set of commands below clones the WR PTP Core
repository, checks out the release tag, and downloads other HDL repositories
repository, checks out the release tag, and downloads other HDL repositories
(
submodules
)
needed to synthesize the core:
(
submodules
)
needed to synthesize the core:
\begin
{
lstlisting
}
\begin
{
lstlisting
}
$
git clone https://ohwr.org/project/wr-cores.git <your
_
location>/wr-cores
$
git clone https://ohwr.org/project/wr-cores.git <your
_
location>/wr-cores
$
cd <your
_
location>
/
wr
-
cores
$
cd <your
_
location>
/
wr
-
cores
$
git checkout wrpc-v
4.1
$
git checkout wrpc-v
5
$
git submodule init
$
git submodule init
$
git submodule update
$
git submodule update
\end{lstlisting}
\end{lstlisting}
...
@@ -446,7 +416,7 @@ Vivado flow to synthesize the bitstream.
...
@@ -446,7 +416,7 @@ Vivado flow to synthesize the bitstream.
\subsection
{
Software compilation
}
\subsection
{
Software compilation
}
\label
{
Software compilation
}
\label
{
Software compilation
}
By default, the
LM32 or the
RISC-V software for a stable release is embedded
By default, the RISC-V software for a stable release is embedded
inside the FPGA bitstream you've downloaded from
\textit
{
ohwr.org
}
or
inside the FPGA bitstream you've downloaded from
\textit
{
ohwr.org
}
or
synthesized in section
\ref
{
HDL synthesis
}
. You can skip this section, unless
synthesized in section
\ref
{
HDL synthesis
}
. You can skip this section, unless
you need to make some custom changes to the soft-core processor's software and
you need to make some custom changes to the soft-core processor's software and
...
@@ -457,58 +427,27 @@ package you will need a \emph{readline-dev} library. In some Linux distributions
...
@@ -457,58 +427,27 @@ package you will need a \emph{readline-dev} library. In some Linux distributions
you would have to install it manually. E.g. in Ubuntu, please install
you would have to install it manually. E.g. in Ubuntu, please install
\emph
{
libreadline-dev
}
package.
\\
\emph
{
libreadline-dev
}
package.
\\
As mentioned in the section
\ref
{
Supported soft-core processors
}
, the WRPC from
the v5.0 release can be build for LM32 or RISC-V soft-core processor. Major
parts of the building process are the same for both architecures.
First, you need to download and unpack the toolchain from the location
First, you need to download and unpack the toolchain from the location
mentioned in section
\ref
{
Repositories and Releases
}
. The following example
mentioned in section
\ref
{
Repositories and Releases
}
.
uses 32bit version of a LM32 toolchain.
\begin{lstlisting}
$
wget https:
//
www.ohwr.org
/
project
/
wrpc
-
sw
/
uploads
/
a
2
e
8
eeba
448
fbc
8
d
580
e
68004
e
6
f
6
c
7
f
/
\
lm
32
.tar.xz
$
tar xJf lm32.tar.xz -C <your
_
location>
\end{lstlisting}
If you encounter problems running it, please use the LM32's 64bit version.
\begin{lstlisting}
$
wget https:
//
www.ohwr.org
/
project
/
wrpc
-
sw
/
uploads
/
2776
ce
0
ba
43503
d
1486
ae
205
b
48
fb
450
/
\
lm
32
_
host
_
64
bit.tar.xz
$
tar xJf lm32
_
host
_
64bit.tar.xz -C <your
_
location>
\end{lstlisting}
If you decide to use RISC-V, please use the following toolchain:
\begin{lstlisting}
\begin{lstlisting}
$
wget https:
//
ohwr.org
/
project
/
wrpc
-
sw
/
wikis
/
uploads
/
e
445916
c
27
cc
49
cc
62
a
370
aded
9
cacb
2
/
\
$
wget https:
//
ohwr.org
/
project
/
wrpc
-
sw
/
wikis
/
uploads
/
9
f
9224
d
2249848
ed
3
e
854636
de
9
c
08
dc
/
\
riscv
_
gcc
_
11
_
1
_
0
.tar.x
z
riscv
-
11
.
2
-
small.tg
z
$
tar xJf riscv
_
gcc
_
11
_
1
_
0.tar.x
z -C <your
_
location>
$
tar xJf riscv
-11.2-small.tg
z -C <your
_
location>
\end{lstlisting}
\end{lstlisting}
Then you need to set a
\texttt
{
CROSS
\_
COMPILE
}
environment variable in order
Then you need to set a
\texttt
{
CROSS
\_
COMPILE
}
environment variable in order
to compile the software. For the LM32 processor:
to compile the software. For the RISC-V processor:
\begin{lstlisting}
$
export CROSS
_
COMPILE
=
"<your
_
location>
/
lm
32
/
bin
/
lm
32
-
elf
-
"
\end
{
lstlisting
}
For the RISC
-
V processor:
\begin
{
lstlisting
}
$
export CROSS
_
COMPILE="<your
_
location>/riscv/bin/riscv32-unknown-elf-"
\end{lstlisting}
Or you can let the build system to select the proper toolchain based on
the selected architecture:
\begin{lstlisting}
\begin{lstlisting}
$
export CROSS
_
COMPILE
_
LM
32
=
"<your
_
location>
/
lm
32
/
bin
/
lm
32
-
elf
-
"
$
export CROSS
_
COMPILE
=
"<your
_
location>
/
riscv
-
11
.
2
-
small
/
bin
/
riscv
32
-
elf
-
"
$
export CROSS
_
COMPILE
_
RISCV="<your
_
location>/riscv/bin/riscv32-unknown-elf-"
\end
{
lstlisting
}
\end
{
lstlisting
}
To get the sources of the WRPC software, please clone the
\textit
{
wrpc
-
sw
}
git
To get the sources of the WRPC software, please clone the
\textit
{
wrpc
-
sw
}
git
repository tagged with
\texttt
{
wrpc
-
v
5
.
0
}
tag. The commands in the listing below
repository tagged with
\texttt
{
wrpc
-
v
5
.
0
}
tag. The commands in the listing below
clone the
\textit
{
wrpc
-
sw
}
repository together with submodules needed for this software.
\\
clone the
\textit
{
wrpc
-
sw
}
repository together with submodules needed for this software.
\\
\begin
{
lstlisting
}
\begin
{
lstlisting
}
$
git clone https://ohwr.org/project/wrpc-sw.git <your
_
location>/wrpc-sw
$
git clone https://ohwr.org/project/wrpc-sw.git <your
_
location>/wrpc-sw
$
cd <your
_
location>
/
wrpc
-
sw
$
cd <your
_
location>
/
wrpc
-
sw
$
git checkout wrpc
-
v
5
.
0
$
git checkout wrpc-v5
\end{lstlisting}
\end{lstlisting}
\textbf
{
Note:
}
If you use WRPC within another project, you may need to checkout
\textbf
{
Note:
}
If you use WRPC within another project, you may need to checkout
...
@@ -534,11 +473,6 @@ three boards mentioned in this manual \code{spec\_defconfig} can be used.
...
@@ -534,11 +473,6 @@ three boards mentioned in this manual \code{spec\_defconfig} can be used.
$
make spec
_
defconfig
$
make spec
_
defconfig
\end
{
lstlisting
}
\end
{
lstlisting
}
Each configuration file includes the definition of the architecture used for
soft-processor. To change it call the configuration tools described above or
manually set configuration options
\texttt
{
CONFIG
\_
ARCH
\_
LM32
}
and
\texttt
{
CONFIG
\_
ARCH
\_
RISCV
}
.
After the package is configured, just run
\code
{
make
}
without parameters to
After the package is configured, just run
\code
{
make
}
without parameters to
build your binary file:
build your binary file:
\begin
{
lstlisting
}
\begin
{
lstlisting
}
...
@@ -724,7 +658,7 @@ where \texttt{xx:xx:xx:xx:xx:xx} is the MAC address of your board.\\
...
@@ -724,7 +658,7 @@ where \texttt{xx:xx:xx:xx:xx:xx} is the MAC address of your board.\\
Next, you should input calibration fixed delays values and alpha parameters. The
Next, you should input calibration fixed delays values and alpha parameters. The
example below clears any existing entries and adds two Axcen transceivers with
example below clears any existing entries and adds two Axcen transceivers with
$
\Delta
_{
TX
}$
,
$
\Delta
_{
RX
}$
and
$
\alpha
$
parameters associated with them.
$
\Delta
_{
TX
}$
,
$
\Delta
_{
RX
}$
and
$
\alpha
$
parameters associated with them.
Please note that the
$
\alpha
$
value is slit into two values. The most
Please note that the
$
\alpha
$
value is s
p
lit into two values. The most
significant
9
decimal digits and the least significant
9
decimal digits.
significant
9
decimal digits and the least significant
9
decimal digits.
\begin
{
lstlisting
}
\begin
{
lstlisting
}
...
@@ -1786,8 +1720,7 @@ To this aim, you can pass a memory image (dump of RAM content) of \textit{wrpc}
...
@@ -1786,8 +1720,7 @@ To this aim, you can pass a memory image (dump of RAM content) of \textit{wrpc}
The tool will print information for softpll, ppsi data structures,
The tool will print information for softpll, ppsi data structures,
ptp data sets and version information.
ptp data sets and version information.
For example, for the
\textit
{
spec
}
board and WRPC using LM
32
as a soft
-
core
For example, for the
\textit
{
spec
}
board, you can use the resource file in
processor, you can use the resource file in
\textit
{
sysfs
}
to look at a live system, or copy the file for off-line
\textit
{
sysfs
}
to look at a live system, or copy the file for off-line
analysis. The following command line show both uses:
analysis. The following command line show both uses:
...
...
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