1. Solve RJ45 related bug.

2. Modify all Reisitor value/package name.

1. Solve RJ45 related bug.
2. Modify all Reisitor value/package name.
bb741616 · hongming · 1f4b3f28 · bb741616 · bb741616 · bb741616
Commit bb741616 authored Apr 22, 2018 by hongming
38 changed files
--- a/.gitignore
+++ b/.gitignore
 *__Previews/
-History/*
+*History*
 Project output *
 *.htm
 Manufacture
\ No newline at end of file
--- a/wrs-backplane-18sfp/pcb/wrs-backplane-18sfp.PcbDoc
+++ b/wrs-backplane-18sfp/pcb/wrs-backplane-18sfp.PcbDoc
--- a/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCB
+++ b/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCB
@@ -30,7 +30,7 @@ DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
 FSMCodingStyle=eFMSDropDownList_OneProcess
 FSMEncodingStyle=eFMSDropDownList_OneHot
-OutputPath=Project Outputs for wrs-backplane-18sfp
+OutputPath=
 LogFolderPath=
 ManagedProjectGUID=
@@ -271,7 +271,7 @@ SCH_ShowNote=-1
 SCH_ShowNoteCollapsed=-1
 [Generic_EDE]
-OutputDir=Project Outputs for wrs-backplane-18sfp
+OutputDir=
 [OutputGroup1]
 Name=Netlist Outputs

--- a/wrs-backplane-18sfp/schematics/wrs_backplane_18SFP.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_backplane_18SFP.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_connector.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_connector.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_link.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_link.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_misc.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_misc.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_usb_dbg.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_usb_dbg.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_usb_to_sfp.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_usb_to_sfp.SchDoc
--- a/wrs-backplane-18sfp/wrs-backplane-18sfp_V1.1.zip
+++ b/wrs-backplane-18sfp/wrs-backplane-18sfp_V1.1.zip
--- a/wrs-fl-hw/PCB-layout/AdditionCard.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/AdditionCard.PcbDoc
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbDoc
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbLib
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbLib
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.2.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.2.PcbDoc
--- a/wrs-fl-hw/Schematics/CDCM61002.SchDoc
+++ b/wrs-fl-hw/Schematics/CDCM61002.SchDoc
--- a/wrs-fl-hw/Schematics/CLK_25M_DMTD.SchDoc
+++ b/wrs-fl-hw/Schematics/CLK_25M_DMTD.SchDoc
--- a/wrs-fl-hw/Schematics/CLK_25M_GTX.SchDoc
+++ b/wrs-fl-hw/Schematics/CLK_25M_GTX.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_100M_Ethernet.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_100M_Ethernet.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_JTAG.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_JTAG.SchDoc
--- a/wrs-fl-hw/Schematics/Connectors.SchDoc
+++ b/wrs-fl-hw/Schematics/Connectors.SchDoc
--- a/wrs-fl-hw/Schematics/DCDC.SchDoc
+++ b/wrs-fl-hw/Schematics/DCDC.SchDoc
--- a/wrs-fl-hw/Schematics/DFF_SYNC.SchDoc
+++ b/wrs-fl-hw/Schematics/DFF_SYNC.SchDoc
--- a/wrs-fl-hw/Schematics/EXT_10M_IN.SchDoc
+++ b/wrs-fl-hw/Schematics/EXT_10M_IN.SchDoc
--- a/wrs-fl-hw/Schematics/EXT_PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/EXT_PLL.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_Configuration.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_Configuration.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_EXT_PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_EXT_PLL.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_GTX.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_GTX.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.SchDoc
--- a/wrs-fl-hw/Schematics/LDO_ALL.SchDoc
+++ b/wrs-fl-hw/Schematics/LDO_ALL.SchDoc
--- a/wrs-fl-hw/Schematics/LDO_XO.SchDoc
+++ b/wrs-fl-hw/Schematics/LDO_XO.SchDoc
--- a/wrs-fl-hw/Schematics/LVPECL_FANOUT.SchDoc
+++ b/wrs-fl-hw/Schematics/LVPECL_FANOUT.SchDoc
--- a/wrs-fl-hw/Schematics/PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/PLL.SchDoc
--- a/wrs-fl-hw/Schematics/PPS.SchDoc
+++ b/wrs-fl-hw/Schematics/PPS.SchDoc
--- a/wrs-fl-hw/Schematics/SENSOR.SchDoc
+++ b/wrs-fl-hw/Schematics/SENSOR.SchDoc
--- a/wrs-fl-hw/Schematics/UART_TO_USB.SchDoc
+++ b/wrs-fl-hw/Schematics/UART_TO_USB.SchDoc
--- a/wrs-fl-hw/wrs-fl-hw_v1.1.PrjPCB
+++ b/wrs-fl-hw/wrs-fl-hw_v1.1.PrjPCB
@@ -872,7 +872,7 @@ GenerateClassCluster=0
 DocumentUniqueId=
 [Document50]
-DocumentPath=PCB-layout\wrs-fl-hw_v1.1.PcbDoc
+DocumentPath=PCB-layout\wrs-fl-hw_v1.2.PcbDoc
 AnnotationEnabled=1
 AnnotateStartValue=1
 AnnotationIndexControlEnabled=0
@@ -888,10 +888,6 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=YYJIREQQ
-[GeneratedDocument1]
-DocumentPath=doc\wrs-fl-hw_v1.1.csv
-DItemRevisionGUID=
 [Parameter1]
 Name=Date
 Value=12/06/2012

--- a/wrs-fl-hw/wrs-fl-hw_v1.1.PrjPCBStructure
+++ b/wrs-fl-hw/wrs-fl-hw_v1.1.PrjPCBStructure