White Rabbit Switch Fan-less hardware
Project description
White Rabbit Switch Fan-less is an open hardware design of an 18-ports Ethernet switch licensed under CERN OHL 1.2. It is a central element of a White Rabbit network and was designed as a part of the White Rabbit project. This is a fan-less version of the WRS 3.4 that is specifically designed for long-term service-less operation and originated at the LHAASO project.
The WR Switch can be used with official firmware releases. As the design is open it can also be used as the hardware platform for other, non-White Rabbit projects.
WR Switch fan-less hardware consists of three elements:
- WR Switch Box - is a white metal 19'' 1U case. There are no cooling fans in the back - This box is specifically designed for passive cooling.
- main PCB - contains main electronics components, ARM processor, Xilinx FPGA chip, oscillators, memories, etc. - This is a redesigned board, different from the one used in the original WRS-3.4.
- backplane PCB - electrical connections to 18 SFP cages, debug USB-uart ports, LEDs, etc. - This board is the same as used in the original WRS-3.4.
Original WR Switch v3.3 top view of PCBs. The fan-less version will
have a different, larger, board on the left and no fans in the back*
Main Features
In bold the features that are different from WRS-3.4
- Front Panel
- 5 SMC connectors
- 1-PPS input and output
- 62.5 MHz output
- 10 MHz output (software configurable)
- 10 MHz input
- Integrated Low-jitter WRS daughterboard for improved clock outputs
- 18 cages for Gigabit SFP transceivers (connected to Xilinx GTXs)
- 10/100 Ethernet management port (connected to ARM CPU) on SFP (was RJ-45 used on WRS-3.4)
- USB-uart management port (connected to ARM CPU)
- Power and Status LEDs
- Link and Act LEDs for each SFP cage
- 5 SMC connectors
- Back Panel
- 2x USB-uart debugging port (connected to ARM CPU and FPGA I/O pins)
- power button
2x cooling fan- removed in fan-less version- -2x microswitch- - removed in fan-less version
- 1x grounding connector
- Xilinx Virtex-6 FPGA (XC6VLX240T)
- Clocking resources
- 1x Low-Jitter Clock Generator (TI CDCM61002, used as DMTD offset clock in WR Switch HDL)
- 1x 25MHz VCXO, FRETHE025 controlled by DAC with SPI interface (AD5662, used to drive CDCM61002 generator)
- 1x 25MHz VCO controlled by DAC with SPI interface (AD5662, used to drive AD9516 generator)
- 1x 25MHz XO oscillator FNETHE025 (main FPGA clock)
- 14-Output Clock Generator with Integrated 1.6 GHz VCO (AD9516, clock signals for Xilinx GTXs, uTCA connectors)
- 1x Internal Oscillator (VM53S3-25.000, tuned to follow WR master clock or followed in Free Running mode)
- ARM Atmel AT91 SAM9G45 CPU
- Memory:
64MB DDR2removed in fan-less version256MB NANDremoved in fan-less version- 8MB boot flash
- Others:
- 1x FPGA JTAG connector
- 1x ARM JTAG connector
- 2x I2C multiplexer (PCA9548A)
- 1x I2C GPIO driver (PCA9554PW, driving Power and Status LEDs on the front panel)
- 9x I2C GPIO driver (PCA9554PW, driving LEDs for each SFP cage)
- Power supply 100-240VAC, 2.0A, 50-60Hz input, 12V DC, 6.66A, 80W output
- Box dimensions 482.8 x 42.34 x 222 mm
- Certification
- IPC-610 Rev E Class 2
- ISO-9001
- ISO-14001
- CE
- RoHS
Project information
- Production documentation
- Firmware - compatible to WRS-3.4
-
Gateware for WR Switch
- compatible to WRS-3.4
-
Software for WR Switch
- compatible to WRS-3.4
- Frequently Asked Questions
Releases
Contacts
Commercial producers
- Planned to be commercially available.
General question about project
- Guanghua Gong - Tsinghua University, Beijing
Status
Date | Event |
21-02-2018 | Start of project |
2 March 2018