SCB
The SCB is the main part of the switch.
The modified SCB is larger than the original one. Together with the space saved from the removed components/connectors, the FPGA has many pcb space around for a larger heat sink.
Clock tree
The clock processing and distribution of the SCB is shown below
Power tree
The power generation circuit has been modified from SCB_v3.4 with more DC/DC rails to reduce overburden power consumption.
Reset tree
The reset/re-configure/re-program signals are connected in the following way
Component replacement
Few components are replaced for wider temperature range or better thermal performance.
SCB_v3.4 | SCB_FL | Note |
MC100LVEP14DT | MC100LVEP111MNG | LvPECL fanout IC, change to 10channel version with QFN package |
MC100EP52DR2 | MC100EP52MNR4G | The DFF change to QFN package |
FNETHE025 | 7N-25.000MBP-T | FPGA 25MHz TCXO, change for wider temp. range |
7M-12.000MAAJ-T | ABM8W-12.0000MHZ | ARM CPU TCXO, change for wider temp. range |
MAX3232CDBR | ICL3232EIBNZ | RS232 driver/receiver for wider temp. range |
CP2102-GM | CP2102N-A01-GQFN28 | CP2102 not recommend for new design. Pin compatible |
Connector signal compatibility
The SCB connects the backplane boards through two 96pins high-speed SAMTEC board-to-board connectors. Few pins of the connectors are different between SCB-V3.4 and SCB-FL as listed below
Pin #n | in SCB_V3.4 | in SCB_FL | Note |
J3-P90/92 | FPGA_USB_Tx/Rx | FAN_CTRL1 /2 | These two pins in V3.4 are actually used to control the fan on backplane. Although the WRS_FL implements no fan, we still keep these pins direct connect to FPGA and named as FAN_CTRL1/2 |
J3-P94/96 | ARM_DEBUG_TXD/RXD | N.C. | These two pins are connected to a USB-UART converter to provide a USB serial port for ARM debug. This circuit is implemented on SCB for WRS_FL. Thus those two pins are left NC |
J2-P1 | RS232_MNG_TxD | N.C. | The RS232_MNG_TxD/RxD are RS232 level signals converted on SCB_v3.4 and directly connected to DB-9 on the back panel. |
J2-P3 | RS232_MNG_RxD | ARM_BOOT_SEL_GPIO | On SCB_FL, those RS232 signals are connected to a UART&PWR_MON header |
J2-P5 | N.C. | SPI_SO | Two signals that may affect the booting sequence are connected instead. |