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White Rabbit Trigger Distribution
Commit 09836380 authored by Tristan Gingold's avatar Tristan Gingold
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Add ether endpoint.

parent 8d46f8a9
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mock-turtle @ a06f916f
Subproject commit 415611092f7591a8221a4392cc91f25b16aeeca6 Subproject commit a06f916fbee322712c5b3bbdf94c617a42bad406
hdl/top/svec/list_tdc_fd/svec_list_top.vhd
View file @ 09836380
...@@ -474,6 +474,16 @@ architecture arch of svec_list_top is ...@@ -474,6 +474,16 @@ architecture arch of svec_list_top is
signal mt_notify_irq : std_logic; signal mt_notify_irq : std_logic;
signal vic_master_irq : std_logic; signal vic_master_irq : std_logic;
-- MT endpoints
signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
signal rmq_endpoint_in : t_mt_rmq_endpoint_iface_in;
-- MT fabric.
signal eth_tx_out : t_wrf_source_out;
signal eth_tx_in : t_wrf_source_in;
signal eth_rx_out : t_wrf_sink_out;
signal eth_rx_in : t_wrf_sink_in;
-- MT Dedicated WB interfaces to FMCs -- MT Dedicated WB interfaces to FMCs
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1); signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1);
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1); signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1);
...@@ -638,20 +648,22 @@ begin -- architecture arch ...@@ -638,20 +648,22 @@ begin -- architecture arch
g_CONFIG => c_MT_CONFIG, g_CONFIG => c_MT_CONFIG,
g_WITH_WHITE_RABBIT => TRUE) g_WITH_WHITE_RABBIT => TRUE)
port map ( port map (
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
sp_master_o => open, sp_master_o => open,
sp_master_i => c_DUMMY_WB_MASTER_IN, sp_master_i => c_DUMMY_WB_MASTER_IN,
dp_master_o => fmc_dp_wb_out, dp_master_o => fmc_dp_wb_out,
dp_master_i => fmc_dp_wb_in, dp_master_i => fmc_dp_wb_in,
host_slave_i => cnx_slave_in(c_WB_SLAVE_MT), rmq_endpoint_o => rmq_endpoint_out,
host_slave_o => cnx_slave_out(c_WB_SLAVE_MT), rmq_endpoint_i => rmq_endpoint_in,
clk_ref_i => clk_ref_125m, host_slave_i => cnx_slave_in(c_WB_SLAVE_MT),
tm_i => tm, host_slave_o => cnx_slave_out(c_WB_SLAVE_MT),
hmq_in_irq_o => mt_hmq_in_irq, clk_ref_i => clk_ref_125m,
hmq_out_irq_o => mt_hmq_out_irq, tm_i => tm,
notify_irq_o => mt_notify_irq, hmq_in_irq_o => mt_hmq_in_irq,
console_irq_o => mt_console_irq); hmq_out_irq_o => mt_hmq_out_irq,
notify_irq_o => mt_notify_irq,
console_irq_o => mt_console_irq);
tm.cycles <= tm_cycles; tm.cycles <= tm_cycles;
tm.tai <= tm_tai; tm.tai <= tm_tai;
...@@ -660,7 +672,45 @@ begin -- architecture arch ...@@ -660,7 +672,45 @@ begin -- architecture arch
tm.aux_locked(1 downto 0) <= tm_clk_aux_locked; tm.aux_locked(1 downto 0) <= tm_clk_aux_locked;
tm.aux_locked(7 downto 2) <= (others => '0'); tm.aux_locked(7 downto 2) <= (others => '0');
-- TODO: add RTQ ports and connect to endpoint cmp_eth_endpoint : entity work.mt_ep_ethernet_single
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
rmq_src_i => rmq_endpoint_out.snk_out(0)(0),
rmq_src_o => rmq_endpoint_in.snk_in(0)(0),
rmq_src_config_i => rmq_endpoint_out.snk_config_out(0)(0),
rmq_src_config_o => rmq_endpoint_in.snk_config_in(0)(0),
rmq_snk_i => rmq_endpoint_out.src_out(1)(0),
rmq_snk_o => rmq_endpoint_in.src_in(1)(0),
rmq_snk_config_i => rmq_endpoint_out.src_config_out(1)(0),
rmq_snk_config_o => rmq_endpoint_in.src_config_in(1)(0),
eth_src_o => eth_tx_out,
eth_src_i => eth_tx_in,
eth_snk_o => eth_rx_out,
eth_snk_i => eth_rx_in
);
rmq_endpoint_in.snk_in(0)(1 to t_maxslot_range'high) <=
(others => c_MT_DUMMY_SINK_IN);
rmq_endpoint_in.snk_config_in(0)(1 to t_maxslot_range'high) <=
(others => c_MT_DUMMY_EP_CONFIG_IN);
rmq_endpoint_in.snk_in(1 to t_maxcpu_range'high) <=
(others => (others => c_MT_DUMMY_SINK_IN));
rmq_endpoint_in.snk_config_in(1 to t_maxcpu_range'high) <=
(others => (others => c_MT_DUMMY_EP_CONFIG_IN));
rmq_endpoint_in.src_in(0) <=
(others => c_MT_DUMMY_SOURCE_IN);
rmq_endpoint_in.src_config_in(0) <=
(others => c_MT_DUMMY_EP_CONFIG_IN);
rmq_endpoint_in.src_in(1)(1 to t_maxslot_range'high) <=
(others => c_MT_DUMMY_SOURCE_IN);
rmq_endpoint_in.src_config_in(1)(1 to t_maxslot_range'high) <=
(others => c_MT_DUMMY_EP_CONFIG_IN);
rmq_endpoint_in.src_in(2 to t_maxcpu_range'high) <=
(others => (others => c_MT_DUMMY_SOURCE_IN));
rmq_endpoint_in.src_config_in(2 to t_maxcpu_range'high) <=
(others => (others => c_MT_DUMMY_EP_CONFIG_IN));
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- The WR PTP core SVEC board package (WB Slave) -- The WR PTP core SVEC board package (WB Slave)
...@@ -717,10 +767,10 @@ begin -- architecture arch ...@@ -717,10 +767,10 @@ begin -- architecture arch
spi_miso_i => spi_miso_i, spi_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC), wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC), wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => open, -- TODO wrf_src_o => eth_rx_in,
wrf_src_i => c_dummy_src_in, -- TODO wrf_src_i => eth_rx_out,
wrf_snk_o => open, -- TODO wrf_snk_o => eth_tx_in,
wrf_snk_i => c_dummy_snk_in, -- TODO wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
......
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