Skip to content

W
White Rabbit Trigger Distribution
Commit 2894733f authored by Federico Vaga's avatar Federico Vaga
Browse files
Options

Merge branch 'proposed_master' into fvaga-proposed_master 

This merges the software changes to make WRTd compile against Mock Turtle 4.0.
This needs also to point to a newer Mock Turtle commit.

During the merge I had to fix Makefile paths to mock-turtle since it has been
moved to the dependencies directory
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parents 7725e6a0 9de10e18
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 777 additions and 136 deletions
.gitmodules
View file @ 2894733f
[submodule "mock-turtle"]
path = mock-turtle
[submodule "dependencies/mock-turtle"]
path = dependencies/mock-turtle
url = git://ohwr.org/hdl-core-lib/mock-turtle.git
[submodule "hdl/ip_cores/mock-turtle"]
path = hdl/ip_cores/mock-turtle
url = git://ohwr.org/hdl-core-lib/mock-turtle.git
[submodule "hdl/ip_cores/fine-delay"]
path = hdl/ip_cores/fine-delay
[submodule "dependencies/fine-delay"]
path = dependencies/fmc-delay-1ns-8cha
url = git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git
[submodule "hdl/ip_cores/fmc-tdc"]
path = hdl/ip_cores/fmc-tdc
[submodule "dependencies/fmc-tdc"]
path = dependencies/fmc-tdc-1ns-5cha-gw
url = git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
[submodule "dependencies/vme64x-core"]
path = dependencies/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
[submodule "dependencies/general-cores"]
path = dependencies/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
[submodule "dependencies/wr-cores"]
path = dependencies/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
[submodule "dependencies/urv-core"]
path = dependencies/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
fmc-delay-1ns-8cha @ 84dca3f5
Subproject commit 84dca3f543664b508445efb56e915275bb02cd19
fmc-tdc-1ns-5cha-gw @ e8245b04
Subproject commit e8245b04c3ba34869487400ac84b90a746cfd95d
general-cores @ 01731cd1
Subproject commit 01731cd1675402d6b2a8139ec7c8ad9bf64a3507
mock-turtle @ 11c33316
File moved
urv-core @ 70e9e78f
Subproject commit 70e9e78f740aa7f4d8168ccaa003bf3924824284
vme64x-core @ 633d3174
File moved
wr-cores @ 02873972
Subproject commit 02873972e7d9984933ad024e98fe32b88787704e
etherbone-core @ f19220ff
Subproject commit f19220ffa3c5e526f66ebbded5e0e1e789e7255d
fine-delay @ 309cd51f
Subproject commit 309cd51f59efc8c10037f220dc22cde73ca9eda9
fmc-tdc @ 8a82e727
Subproject commit 8a82e727483b3e65771c7a36d1371aba24a6db98
general-cores @ 0545c25b
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
mock-turtle @ 41561109
Subproject commit 415611092f7591a8221a4392cc91f25b16aeeca6
urv-core @ 890dfda6
Subproject commit 890dfda6d8a9de5a1cf7e3aa49304d3778745cb0
wr-cores @ 2573b6cd
Subproject commit 2573b6cd58732813593e12e3144ff8c87955228c
hdl/syn/svec/list_tdc_fd/Manifest.py
View file @ 2894733f
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
......@@ -8,12 +14,16 @@ syn_top = "svec_list_top"
syn_project = "svec_list_tdc_fd.xise"
syn_tool ="ise"
fetchto = "../../../ip_cores"
fetchto = "../../../../dependencies"
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
files = [
"svec_list_top.ucf",
]
modules = {
"local" : [
"../../../top/svec/list_tdc_fd",
......
hdl/top/svec/list_tdc_fd/svec_list_top.ucf → hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
View file @ 2894733f
......@@ -701,35 +701,28 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# relax all paths through syncrhonisers
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
TIMESPEC TS_crossdomain_1 = FROM "clk_sys" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_2 = FROM "clk_125m_pllref" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_3 = FROM "clk_sys" TO "phy_rx_rbclk" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_4 = FROM "phy_rx_rbclk" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "clk_125m_pllref" TO "phy_rx_rbclk" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_6 = FROM "phy_rx_rbclk" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_7 = FROM "clk_sys" TO "tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_8 = FROM "tdc_clk_125m" TO "clk_sys" 20ns DATAPATHONLY;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMESPEC TS_crossdomain_9 = FROM "clk_sys" TO "dcm1_clk_ref_0" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_10 = FROM "dcm1_clk_ref_0" TO "clk_sys" 20ns DATAPATHONLY;
TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
TIMESPEC TS_crossdomain_11 = FROM "clk_125m_pllref" TO "dcm1_clk_ref_0" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_12 = FROM "dcm1_clk_ref_0" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "synchronizers" 16ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_crossdomain_13 = FROM "clk_125m_pllref" TO "tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_14 = FROM "tdc_clk_125m" TO "clk_125m_pllref" 20ns DATAPATHONLY;
# one more path where TAI time crosses from WR ref to MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
NET "*/gc_sync_register_in[*]" MAXDELAY=4ns;
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 16ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
......
hdl/testbench/Makefile 0 → 100644
View file @ 2894733f
# This Makefile can be called by the Continuous Integration (CI) tool to execute all
# testbenches added for CI
#
# Author: Adam Wujek, CERN 2017
TB_DIRS=wrtd-system
test_results_xml=test_results.xml
.PHONY: $(TB_DIRS)
all: $(TB_DIRS) summary summary_total summary_xml
FW_RMQ_UDP_BIN = ../../tests/firmware/rmq-udp/fw-rmq-udp.bin
wrtd-system: $(FW_RMQ_UDP_BIN)
$(FW_RMQ_UDP_BIN):
$(MAKE) -C $(@D) defconfig
$(MAKE) -C $(@D)
$(TB_DIRS):
@echo $@
@echo "Run HDL-MAKE"
cd "$@"; \
$(HDLMAKE_PATH)/hdl-make 2>&1
@echo "Run make"
$(MAKE) -C $@ $(TARGET) -j 1
@echo "Run vsim"
cd "$@" ;\
vsim -c -do "run_ci.do" -l transcript."$@".txt;\
echo "vsim returned $$?"
summary: $(TB_DIRS)
@echo "-------------------------------------------------------------------"
@echo "Summary:"
@for d in $(TB_DIRS); do \
if [ -f $$d/transcript."$$d".txt ]; then \
echo "Warnings for $$d:"; \
cat $$d/transcript."$$d".txt | grep Warning:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
echo "Errors for $$d:"; \
cat $$d/transcript."$$d".txt | grep Error:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
echo "Fatals for $$d:"; \
cat $$d/transcript."$$d".txt | grep Fatal:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
else \
echo "No transcript file for $$d"; \
fi \
done
# Run tasks all before summary_total, because if there is a failure summary_total breaks the make execution
summary_total: summary summary_xml
@echo "-------------------------------------------------------------------"
@echo ""
@echo "Summary total:"
@echo "+---------------------------------------------------+----------+----------+----------+"
@echo "| Test bench | Warnings | Errors | Fatals |"
@echo "+---------------------------------------------------+----------+----------+----------+"
@is_error=0;\
for d in $(TB_DIRS); do \
if [ -f $$d/transcript."$$d".txt ]; then \
printf "| %-50s" $$d; \
printf "| %8d " `cat $$d/transcript."$$d".txt | grep Warning: | wc -l`; \
error_n=`cat $$d/transcript."$$d".txt | grep Error: | wc -l`; \
printf "| %8d " $$error_n;\
if [ $$error_n -gt 0 ]; then is_error=1; fi ;\
fatal_n=`cat $$d/transcript."$$d".txt | grep Fatal: | wc -l`; \
printf "| %8d |\n" $$fatal_n;\
if [ $$fatal_n -gt 0 ]; then is_error=1; fi ;\
else \
printf "| %-30s" $$d; \
echo "| No transcript file! |"; is_error=1; \
fi \
done ;\
echo "+---------------------------------------------------+----------+----------+----------+";\
if [ $$is_error -gt 0 ]; then exit 1; fi ;
summary_xml: summary
@echo '<?xml version="1.0" encoding="UTF-8"?>' > $(test_results_xml)
@echo '<testsuites tests="0" failures="0" disabled="0" errors="0" time="0" name="AllTests">' >> $(test_results_xml)
@for d in $(TB_DIRS); do \
is_test_error=0;\
error_n=0;\
fatal_n=0;\
echo -n " <testsuite name=\""$$d"\" tests=\"1\" failures=\"" >> $(test_results_xml) ;\
if [ -f $$d/transcript."$$d".txt ]; then \
error_n=`cat $$d/transcript."$$d".txt | grep Error: | wc -l`; \
fatal_n=`cat $$d/transcript."$$d".txt | grep Fatal: | wc -l`; \
if [ $$error_n -gt 0 ] || [ $$fatal_n -gt 0 ]; then is_test_error=1; fi ;\
echo -n $$is_test_error >> $(test_results_xml);\
else \
is_test_error=2; \
echo -n "1" >> $(test_results_xml); \
fi; \
echo "\" disabled=\"0\" errors=\"0\" time=\"0\">" >> $(test_results_xml) ;\
echo " <testcase name=\""$$d"\" status=\"run\" time=\"0\" classname=\""Testbench"\">" >> $(test_results_xml) ;\
if [ $$is_test_error -eq 1 ]; then \
if [ $$error_n -gt 0 ]; then \
echo " <failure message=\"Errors\" type=\"\"><![CDATA[" >> $(test_results_xml) ;\
cat $$d/transcript."$$d".txt | grep Error: >> $(test_results_xml);\
echo " ]]></failure>" >> $(test_results_xml) ;\
fi;\
if [ $$fatal_n -gt 0 ]; then \
echo " <failure message=\"Fatals\" type=\"\"><![CDATA[" >> $(test_results_xml) ;\
cat $$d/transcript."$$d".txt | grep Fatal: >> $(test_results_xml);\
echo " ]]></failure>" >> $(test_results_xml) ;\
fi;\
fi ;\
if [ $$is_test_error -eq 2 ]; then \
echo " <failure message=\"Output file not found\" type=\"\">" >> $(test_results_xml) ;\
echo "<![CDATA[Output file not found. Testbench didnt run.]]>" >> $(test_results_xml) ;\
echo " </failure>" >> $(test_results_xml) ;\
fi ;\
echo " </testcase>" >> $(test_results_xml) ;\
echo " </testsuite>" >> $(test_results_xml) ;\
done ;\
echo "</testsuites>" >> $(test_results_xml)
clean:
@for d in $(TB_DIRS); do \
if [ -f $$d/Makefile ]; then \
$(MAKE) -C $$d $@; \
rm -f $$d/Makefile; \
fi \
done
hdl/testbench/wrtd-system/.gitignore 0 → 100644
View file @ 2894733f
work/
Makefile
modelsim.ini
transcript*
*.wlf
hdl/testbench/wrtd-system/Manifest.py 0 → 100644
View file @ 2894733f
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
board = "svec"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
fetchto="../../../dependencies"
include_dirs = [
fetchto + "/mock-turtle/hdl/testbench/include/",
fetchto + "/mock-turtle/hdl/testbench/include/regs/",
fetchto + "/general-cores/sim/",
fetchto + "/urv-core/rtl/",
]
files = [
"main.sv",
"synthesis_descriptor.vhd",
]
modules = {
"local" : [
"../../top/svec/list_tdc_fd",
],
}
hdl/testbench/wrtd-system/main.sv 0 → 100644
View file @ 2894733f
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// LHC Instability Trigger Distribution (LIST)
// https://ohwr.org/projects/list
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: A SystemVerilog testbench to exercise all the main features of
// LIST
//
//------------------------------------------------------------------------------
// Copyright CERN 2018
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`include "mock_turtle_driver.svh"
`include "vhd_wishbone_master.svh"
`timescale 1ns/10fs
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
reg clk_ext = 0;
wire a2btxp, a2btxn, b2atxp, b2atxn;
always #50ns clk_ext <= ~clk_ext;
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
initial begin
repeat(20) @(posedge clk_20m_vcxo);
rst_n = 1;
end
svec_list_top #
(
.g_simulation (1),
.g_sim_bypass_vme (1),
.g_dpram_initf("../../ip_cores/wr-cores/bin/wrpc/wrc_phy8_sim.bram")
)
DUT_A
(
.rst_n_i (rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_125m_gtp_p_i (clk_125m_pllref),
.clk_125m_gtp_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (clk_20m_vcxo),
.sim_wb_i (HostA.out),
.sim_wb_o (HostA.in),
.sfp_txp_o (a2btxp),
.sfp_txn_o (a2btxn),
.sfp_rxp_i (b2atxp),
.sfp_rxn_i (b2atxn)
);
IVHDWishboneMaster HostA
(
.clk_i (DUT_A.clk_sys_62m5),
.rst_n_i (DUT_A.rst_sys_62m5_n));
IMockTurtleIRQ IrqMonitorA (`MT_ATTACH_IRQ(DUT_A.cmp_mock_turtle));
svec_list_top #
(
.g_simulation (1),
.g_sim_bypass_vme (1),
.g_dpram_initf("../../ip_cores/wr-cores/bin/wrpc/wrc_phy8_sim.bram")
)
DUT_B
(
.rst_n_i (rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_125m_gtp_p_i (clk_125m_pllref),
.clk_125m_gtp_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (clk_20m_vcxo),
.sim_wb_i (HostB.out),
.sim_wb_o (HostB.in),
.sfp_txp_o (b2atxp),
.sfp_txn_o (b2atxn),
.sfp_rxp_i (a2btxp),
.sfp_rxn_i (a2btxn)
);
IVHDWishboneMaster HostB
(
.clk_i (DUT_B.clk_sys_62m5),
.rst_n_i (DUT_B.rst_sys_62m5_n));
IMockTurtleIRQ IrqMonitorB (`MT_ATTACH_IRQ(DUT_B.cmp_mock_turtle));
string fw = "../../../tests/firmware/rmq-udp/fw-rmq-udp.bin";
const uint64_t mt_base = 'h2_0000;
MockTurtleDriver drvA, drvB;
initial begin
@(posedge DUT_A.rst_sys_62m5_n);
@(posedge DUT_A.clk_sys_62m5);
drvA = new (HostA.get_accessor(), mt_base, IrqMonitorA, "DUTA");
drvB = new (HostB.get_accessor(), mt_base, IrqMonitorB, "DUTB");
drvA.init();
drvB.init();
drvA.enable_console_irq (0, 1);
drvB.enable_console_irq (1, 1);
drvA.load_firmware(0, fw, 1'b0);
drvB.load_firmware(1, fw, 1'b0);
drvA.reset_core(0, 0);
drvB.reset_core(1, 0);
forever begin
drvA.update ();
drvB.update ();
#1us;
end
end // initial begin
/// ////////////////////////////////////////////////////////////////////////
/// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
/// ////////////////////////////////////////////////////////////////////////
initial begin
force DUT_A.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT_A.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT_A.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
force DUT_B.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT_B.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT_B.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end
endmodule // main
hdl/testbench/wrtd-system/run.do 0 → 100644
View file @ 2894733f
vsim -quiet -L unisim work.main -novopt -suppress 8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
run 300us
hdl/testbench/wrtd-system/run_ci.do 0 → 100644
View file @ 2894733f
# Modelsim run script for continuous integration
# execute: vsim -c -do "run_ci.do"
vsim -quiet -L unisim work.main -suppress 8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run 800us
exit
hdl/testbench/wrtd-system/synthesis_descriptor.vhd 0 → 100644
View file @ 2894733f
--------------------------------------------------------------------------------
-- SDB meta information for svec_list_tdc_fd.xise.
--
-- This file was automatically generated by ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Friday, July 20 2018
--
-- ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := (
syn_module_name => "svec_list_tdc_fd",
syn_commit_id => "4a68a12eede44d878435d25c3c7eaaf4",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20180720",
syn_username => "Dimitris Lampri");
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "ssh://git@gitlab.cern.ch:7999/coht/wr-trigger-distribution.git ");
end package synthesis_descriptor;
hdl/top/svec/list_tdc_fd/Manifest.py
View file @ 2894733f
files = [
"svec_list_top.vhd",
"svec_list_top.ucf",
]
fetchto = "../../../ip_cores"
fetchto = "../../../../dependencies"
modules = {
"local" : [ "../../../ip_cores/mock-turtle/hdl/rtl",
"../../../ip_cores/wr-cores/board/svec",
"../../../ip_cores/fine-delay/hdl",
"../../../ip_cores/fmc-tdc/hdl/rtl",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
],
}
hdl/top/svec/list_tdc_fd/svec_list_top.vhd
View file @ 2894733f
This diff is collapsed.
software/Makefile
View file @ 2894733f
......@@ -6,7 +6,7 @@ REPO_PARENT=..
.PHONY: all clean modules install modules_install clean_all
.PHONY: gitmodules prereq prereq_install prereq_install_warn prereq_clean
DIRS = ../mock-turtle/software lib tools rt unittest
DIRS = ../dependencies/mock-turtle/software lib tools rt unittest
all clean modules install modules_install: gitmodules
for d in $(DIRS); do $(MAKE) -C $$d $@ || exit 1; done
software/firmware/fd/Makefile
View file @ 2894733f
......@@ -5,7 +5,7 @@ OBJS += common/wrtd-fw-common.o
OBJS += common/loop-queue.o
OBJDIR += common
OUTPUT = wrtd-rt-fd
TRTL ?= ../../../mock-turtle/
TRTL ?= ../../../dependencies/mock-turtle/
TRTL_SW = $(TRTL)/software
EXTRA_CFLAGS += -I../../include
......
software/firmware/tdc/Makefile
View file @ 2894733f
......@@ -6,7 +6,7 @@ OBJS += common/loop-queue.o
OBJDIR += common
OUTPUT = wrtd-rt-tdc
TRTL ?= ../../../mock-turtle/
TRTL ?= ../../../dependencies/mock-turtle/
TRTL_SW = $(TRTL)/software
EXTRA_CFLAGS += -I../../include
......
software/lib/Makefile
View file @ 2894733f
......@@ -8,7 +8,7 @@
REPO_PARENT=..
-include $(REPO_PARENT)/parent_common.mk
TRTL ?= ../../mock-turtle/software
TRTL ?= ../../dependencies/mock-turtle/software
LIBTDC ?= ../../fmc-tdc-sw/lib
LIBFD ?= ../../fine-delay-sw/lib
......
software/tools/Makefile
View file @ 2894733f
......@@ -10,7 +10,7 @@ REPO_PARENT=..
DESTDIR ?= /usr/local
TRTL ?= ../../mock-turtle/software
TRTL ?= ../../dependencies/mock-turtle/software
CFLAGS += -Wall -Werror -ggdb
CFLAGS += -I. -I../include -I$(TRTL)/include -I$(TRTL)/lib -I../lib
......
software/unittest/Makefile
View file @ 2894733f
......@@ -8,7 +8,7 @@
REPO_PARENT=..
-include $(REPO_PARENT)/parent_common.mk
TRTL ?= ../mock-turtle
TRTL ?= ../../dependencies/mock-turtle/software
CFLAGS += -Wall -ggdb -O0
CFLAGS += -I. -I../include -I$(TRTL)/include -I$(TRTL)/lib -I../lib
......
tests/firmware/.gitignore 0 → 100644
View file @ 2894733f
*.elf
*.bin
*.o
*.d
build/
.config
.config.old
tests/firmware/Makefile 0 → 100644
View file @ 2894733f
-include Makefile.specific
DIRS := rmq-udp
TRTL ?= ../..
TRTL_SW = $(TRTL)/software
all clean cleanall modules install modules_install: $(DIRS)
clean: TARGET = clean
cleanall: TARGET = cleanall
modules: TARGET = modules
install: TARGET = install
modules_install: TARGET = modules_install
DOT-CONFIGS = $(addsuffix /.config,$(DIRS))
$(DIRS): $(DOT-CONFIGS)
$(MAKE) -C $@ $(TARGET)
$(DOT-CONFIGS):
$(MAKE) -C $(@D) defconfig
compare_size:
$(TRTL_SW)/tools/compare_size.sh
.PHONY: all clean cleanall modules install modules_install
.PHONY: $(DIRS)
tests/firmware/rmq-udp/Kconfig 0 → 100644
View file @ 2894733f
mainmenu "rmq_udp_send test configuration"
comment "Project specific configuration"
config FPGA_APPLICATION_ID
int "FPGA application ID"
default 0
help
Help text
config RT_APPLICATION_ID
int "RT application ID"
default 0
help
Help text
# include Mock Turtle's Kconfig
source "Kconfig.mt"
tests/firmware/rmq-udp/Makefile 0 → 100644
View file @ 2894733f
-include ../Makefile.specific
OBJS = rmq-udp.o
OBJS += # add other object files that you need
OUTPUT = fw-rmq-udp
TRTL ?= ../../../dependencies/mock-turtle
TRTL_SW = $(TRTL)/software
CFLAGS_OPT = -O0 # disable optimization
include $(TRTL_SW)/firmware/Makefile
tests/firmware/rmq-udp/configs/mt_defconfig 0 → 100644
View file @ 2894733f
#
# Automatically generated file; DO NOT EDIT.
# rmq_udp_send test configuration
#
#
# Project specific configuration
#
CONFIG_FPGA_APPLICATION_ID=0
CONFIG_RT_APPLICATION_ID=0
#
# Mock Turtle configuration
#
CONFIG_CFLAGS_OPT="-Os"
CONFIG_CFLAGS_EXTRA="-ggdb"
#
# Mock Turtle framework configuration
#
# CONFIG_MOCKTURTLE_FRAMEWORK_ENABLE is not set
# CONFIG_MOCKTURTLE_FRAMEWORK_ACTION_ENABLE is not set
#
# Mock Turtle library configuration
#
CONFIG_MOCKTURTLE_LIBRARY_PRINT_ENABLE=y
# CONFIG_MOCKTURTLE_LIBRARY_PRINT_DEBUG_ENABLE is not set
# CONFIG_MOCKTURTLE_LIBRARY_PRINT_ERROR_ENABLE is not set
# CONFIG_MOCKTURTLE_LIBRARY_PRINT_MESSAGE_ENABLE is not set
tests/firmware/rmq-udp/rmq-udp.c 0 → 100644
View file @ 2894733f
#include <mockturtle-rt.h>
#define MT_WR_LINK_READY (MT_CPU_LR_WR_STAT_LINK_OK | MT_CPU_LR_WR_STAT_TIME_OK)
void send_pkt(int rmq)
{
struct trtl_fw_msg msg;
// queue full? wait
while (!mq_claim(TRTL_RMQ, rmq))
;
mq_map_out_message(TRTL_RMQ, rmq, &msg);
msg.header->len = 1;
*(int *)msg.payload = 0x12345678;
pp_printf ("TX data\n");
mq_send(TRTL_RMQ, rmq);
}
void handle_rx(int rmq)
{
struct trtl_fw_msg tmsg;
while (!mq_poll_in(TRTL_RMQ, 1 << rmq))
;
mq_map_in_message(TRTL_RMQ, rmq, &tmsg);
pp_printf ("RX data: 0x%08x\n", *(int *)tmsg.payload);
mq_discard(TRTL_RMQ, rmq);
}
int main(void)
{
int cpu = trtl_get_core_id();
int rmq = 0;
struct trtl_ep_address bind_addr;
pp_printf("TEST for: RMQ UDP %s\n", cpu == 1 ? "recv" : "send");
while ((lr_readl(MT_CPU_LR_REG_WR_STAT) & MT_WR_LINK_READY) != MT_WR_LINK_READY)
;
pp_printf("WR link up and time valid\n");
// set up the RMQ Endpoint
// we operate only with UDP frames
bind_addr.type = TRTL_EP_FRAME_UDP;
// destination MAC: we use broadcast
bind_addr.dst_mac[0] = 0xff;
bind_addr.dst_mac[1] = 0xff;
bind_addr.dst_mac[2] = 0xff;
bind_addr.dst_mac[3] = 0xff;
bind_addr.dst_mac[4] = 0xff;
bind_addr.dst_mac[5] = 0xff;
// destination port
bind_addr.dst_port = 12345;
// source port
bind_addr.src_port = 7777;
// destination IP: 192.168.90.255 (broadcast)
bind_addr.dst_ip = 0xC0A85AFF;
// source IP: 192.168.90.17
bind_addr.src_ip = 0xC0A85A11;
bind_addr.ethertype = 0x800; // IPv4
// RX filter: we want only UDP packets with matching desination port & IP address.
bind_addr.filter = TRTL_EP_FILTER_UDP | TRTL_EP_FILTER_DST_PORT | TRTL_EP_FILTER_DST_IP;
bind_addr.filter |= TRTL_EP_FILTER_ENABLE;
if (cpu == 1)
{
// configure incoming channel
mq_bind(TRTL_RMQ, rmq, 0, &bind_addr);
}
else
{
// configure outgoing channel
mq_bind(TRTL_RMQ, rmq, 1, &bind_addr);
}
if (cpu == 1) {
while (1)
handle_rx(rmq);
}
else {
send_pkt(rmq);
}
while (1)
;
return 0;
}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment