Rework builder for adc.

2a34d662 · Tristan Gingold · 7386187c · 2a34d662 · 2a34d662 · 2a34d662
Commit 2a34d662 authored Dec 05, 2018 by Tristan Gingold
12 changed files
--- a/builder/fmc-adc-100m14b4cha/config.yaml
+++ b/builder/fmc-adc-100m14b4cha/config.yaml
+repo:
+   "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
+bus:
+   input:
+      "wb_adc{n}_trigin_slave"
+   output:
+      "wb_adc{n}_trigout_slave"
--- a/builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
+++ b/builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
--- a/builder/fmc-adc-100m14b4cha/top.vhd
+++ b/builder/fmc-adc-100m14b4cha/top.vhd
--- a/builder/fmc-delay-1ns-8cha/svec-fmc0.ucf
+++ b/builder/fmc-delay-1ns-8cha/svec-fmc0.ucf
@@ -193,3 +193,7 @@ NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";

 NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
 TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
+
+NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
+TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
+TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
--- a/builder/fmc-delay-1ns-8cha/svec-fmc1.ucf
+++ b/builder/fmc-delay-1ns-8cha/svec-fmc1.ucf
@@ -190,3 +190,7 @@ NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";

 NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
 TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
+
+NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
+TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
+TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
--- a/builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf
+++ b/builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf
@@ -148,3 +148,6 @@ NET "fmc0_tdc_onewire_b" IOSTANDARD = "LVCMOS25";

 NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
 TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
+NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
+TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
+TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
--- a/builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf
+++ b/builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf
@@ -140,3 +140,7 @@ NET "fmc1_tdc_onewire_b" IOSTANDARD = LVCMOS25;

 NET "fmc1_tdc_125m_clk_n_i" TNM_NET = fmc1_tdc_125m_clk_n_i;
 TIMESPEC TS_fmc1_tdc_125m_clk_n_i = PERIOD "fmc1_tdc_125m_clk_n_i" 8 ns HIGH 50%;
+
+NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
+TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
+TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
--- a/builder/svec/fmcs.ucf
+++ b/builder/svec/fmcs.ucf
-NET "fmc{n}_clk_125m" TNM_NET = fmc{n}_clk_125m;
-TIMEGRP "fmc{n}_sync"="synchronizers" EXCEPT "fmc{n}_clk_125m";
-TIMESPEC TS_fmc{n}_sync_ffs = FROM fmc{n}_clk_125m TO "fmc{n}_sync" 20ns DATAPATHONLY;
--- a/builder/svec/top.ucf
+++ b/builder/svec/top.ucf
@@ -360,6 +360,13 @@ NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
 NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
 NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";

+#----------------------------------------
+# IOBs
+#----------------------------------------
+
+# Force PPS output to always be placed as IOB register
+INST "cmp_xwrc_board_svec/*/wrapped_ppsgen/pps_out_o" IOB = FORCE;
+
 #===============================================================================
 # Timing constraints and exceptions
 #===============================================================================
@@ -375,46 +382,63 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
 NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
 TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;

+NET "cmp_xwrc_board_svec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
+TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
+
 NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
 TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;

-# relax all paths through syncrhonisers:
-# 1. define groups for each clock domain
-# 2. define group for all sync chains
-# 3. create sync chain groups that exclude one clock domain each
-# 4. relax path from each clock domain to respective sync chain group
+#----------------------------------------
+# WR DMTD tweaks
+#----------------------------------------

-NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
-NET "clk_sys_62m5" TNM_NET = clk_sys;
-NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in"      TNM = skew_limit;

-NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
-NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
-TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
+TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
+
+#----------------------------------------
+# Asynchronous resets
+#----------------------------------------
+
+# Ignore async reset inputs to reset synchronisers
+NET "*/gc_reset_async_in" TIG;
+
+#----------------------------------------
+# Cross-clock domain sync
+#----------------------------------------
+
+# Declaration of domains
+NET "clk_sys_62m5"                             TNM_NET = sys_clk_62_5;
+NET "clk_ref_125m"                             TNM_NET = clk_125m_pllref;
+NET "clk_ddr_333m"                             TNM_NET = ddr_clk_333m;
+NET "cmp_xwrc_board_svec/clk_pll_dmtd"         TNM_NET = clk_dmtd;
+NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk"   TNM_NET = phy_clk;

-TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_125m_pllref";
-TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys";
-TIMEGRP "phy_sync"="synchronizers" EXCEPT "phy_rx_rbclk";
+TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";

-TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
-TIMESPEC TS_sys_sync_ffs = FROM clk_sys         TO "sys_sync" 20ns DATAPATHONLY;
-TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk    TO "phy_sync" 20ns DATAPATHONLY;
+# Exceptions for crossings via gc_sync_ffs
+NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";

-# Relax the path where TAI time crosses from WR ref to MT sys clock
-# This is already synced via a gc_pulse_synchronizer, which makes sure that
-# TAI WR ref value is stable when sampled by the MT sys clock
-NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
+TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
+TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
+TIMEGRP "phy_sync_ffs"  = "sync_ffs" EXCEPT "phy_clk";

-TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 20ns DATAPATHONLY;
+TIMESPEC TS_sys_sync_ffs  = FROM sys_clk   TO "sys_sync_ffs"  TIG;
+TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd  TO "dmtd_sync_ffs" TIG;
+TIMESPEC TS_phy_sync_ffs  = FROM phy_clk   TO "phy_sync_ffs"  TIG;
+
+# Exceptions for crossings via gc_sync_register
+NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";

-# Relax timing from spll_aligner outputs cref and cin (driven by ref clock)
-# to the spll registers (driven by sys clock). The two sides are already sychronized
-# via a gc_pulse_synchronizer, which makes sure that cref and cin are stable
-# when sampled by the sys clock.
-NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cref(*)" TNM_NET = "wr_spll_sync";
-NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cin(*)"  TNM_NET = "wr_spll_sync";
+TIMEGRP "sys_sync_reg"  = "sync_reg" EXCEPT "sys_clk";
+TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
+TIMEGRP "phy_sync_reg"  = "sync_reg" EXCEPT "phy_clk";

-TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 20ns DATAPATHONLY;
+TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5    TO "sys_sync_reg"  16ns DATAPATHONLY;
+TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg"  8ns  DATAPATHONLY;
+TIMESPEC TS_dmtd_sync_reg     = FROM clk_dmtd        TO "dmtd_sync_reg" 16ns DATAPATHONLY;
+TIMESPEC TS_phy_sync_reg      = FROM phy_clk         TO "phy_sync_reg"  8ns  DATAPATHONLY;

 # External async resets
 NET "rst_n_i" TIG;

--- a/builder/svec/top.vhd
+++ b/builder/svec/top.vhd
@@ -39,6 +39,8 @@ use work.wr_fabric_pkg.all;
 use work.mt_mqueue_pkg.all;
 use work.mock_turtle_pkg.all;
 use work.synthesis_descriptor.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
 {use}

 library unisim;
@@ -201,6 +203,11 @@ architecture arch of {name}_top is
  -- Constants
  -----------------------------------------------------------------------------

+  -- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
+  constant c_WRPC_PLL_CONFIG : t_px_pll_cfg := (
+    enabled => TRUE, divide => 3, multiply => 8 );
+
+
  -- Number of masters attached to the primary wishbone crossbar
  constant c_NUM_WB_MASTERS : integer := 1;

@@ -281,10 +288,11 @@ architecture arch of {name}_top is
  attribute keep                   : string;
  attribute keep of clk_sys_62m5   : signal is "TRUE";
  attribute keep of clk_ref_125m   : signal is "TRUE";
-  attribute keep of clk_ddr_333m : signal is "TRUE";
+  attribute keep of clk_ddr_333m   : signal is "TRUE";
  attribute keep of fmc0_clk_125m  : signal is "TRUE";
  attribute keep of fmc1_clk_125m  : signal is "TRUE";
-
+  attribute keep of rst_ddr_333m_n : signal is "TRUE";
+  
  -- I2C EEPROM
  signal eeprom_sda_in  : std_logic;
  signal eeprom_sda_out : std_logic;
@@ -580,9 +588,12 @@ begin  -- architecture arch

  cmp_xwrc_board_svec : xwrc_board_svec
    generic map (
-      g_simulation  => g_simulation,
-      g_dpram_initf => g_WR_DPRAM_INITF,
-      g_aux_clks    => 2)
+      g_simulation     => g_simulation,
+      g_WITH_EXTERNAL_CLOCK_INPUT => True,
+      g_dpram_initf    => g_WR_DPRAM_INITF,
+      g_AUX_PLL_CONFIG => c_WRPC_PLL_CONFIG,
+      g_fabric_iface   => PLAIN,
+      g_aux_clks       => 2)
    port map (
      clk_20m_vcxo_i       => clk_20m_vcxo_i,
      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
@@ -591,6 +602,7 @@ begin  -- architecture arch
      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,

      clk_10m_ext_i        => clk_ext_ref,
+      pps_ext_i            => pps_ext_in,
      clk_aux_i(0)         => fmc0_clk_125m,
      clk_aux_i(1)         => fmc1_clk_125m,

@@ -649,7 +661,6 @@ begin  -- architecture arch
      tm_dac_wr_o          => tm_dac_wr,
      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
      tm_clk_aux_locked_o  => tm_clk_aux_locked,
-      pps_ext_i            => pps_ext_in,

      pps_p_o              => pps,
      pps_led_o            => pps_led,

--- a/builder/wrtd_builder.py
+++ b/builder/wrtd_builder.py
--- a/configs/adc.yaml
+++ b/configs/adc.yaml
@@ -8,6 +8,7 @@ wrtd-board:
   shared_memsize: 1     # in KB
   0:
     inputs: [ 0 ]
+     outputs: [ 0 ]
     memsize: 32        # in KB
     rules: 16
     alarms: 1