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White Rabbit Trigger Distribution
Commit 42ee5732 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: add generics to initialise the instrunction RAMs of the MT CPUs

parent ac5ad82f
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Showing with 8 additions and 4 deletions
fmc-tdc-1ns-5cha-gw @ 4db629ed
Subproject commit e8245b04c3ba34869487400ac84b90a746cfd95d
Subproject commit 4db629ed018e3796834044803a438bb0a52250f2
general-cores @ 2ae9da74
Subproject commit 7faa55fe373b380665dac981b572867d74a8ed6a
Subproject commit 2ae9da74ef45bdc58d05dc32e1e244563ff5e01f
hdl/top/svec/list_tdc_fd/svec_list_top.vhd
View file @ 42ee5732
......@@ -47,7 +47,9 @@ use unisim.vcomponents.all;
entity svec_list_top is
generic (
g_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_WR_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../../software/firmware/fd/wrtd-rt-fd.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
......@@ -671,6 +673,8 @@ begin -- architecture arch
cmp_mock_turtle : entity work.mock_turtle_core
generic map (
g_CONFIG => c_MT_CONFIG,
g_CPU0_IRAM_INITF => g_MT_CPU0_INITF,
g_CPU1_IRAM_INITF => g_MT_CPU1_INITF,
g_WITH_WHITE_RABBIT => TRUE)
port map (
clk_i => clk_sys_62m5,
......@@ -741,7 +745,7 @@ begin -- architecture arch
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => g_simulation,
g_dpram_initf => g_dpram_initf,
g_dpram_initf => g_WR_DPRAM_INITF,
g_aux_clks => 2)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
......
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