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White Rabbit Trigger Distribution
Commit 47a61400 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: cleanup tab characters in simulations

parent 8c8e6bf0
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Showing with 512 additions and 512 deletions
hdl/testbench/include/wrtd_definitions.svh
View file @ 47a61400
...@@ -111,8 +111,8 @@ class WrtdTstamp; ...@@ -111,8 +111,8 @@ class WrtdTstamp;
protected uint32_t frac; protected uint32_t frac;
function new ( uint32_t seconds = 0, function new ( uint32_t seconds = 0,
uint32_t ns = 0, uint32_t ns = 0,
uint32_t frac = 0 ); uint32_t frac = 0 );
set ( seconds, ns, frac ); set ( seconds, ns, frac );
endfunction // new endfunction // new
...@@ -172,12 +172,12 @@ class WrtdId; ...@@ -172,12 +172,12 @@ class WrtdId;
function void set ( string id ); function void set ( string id );
if ( id.len() > `WRTD_ID_LEN ) if ( id.len() > `WRTD_ID_LEN )
$error ( "length of string longer than the available storage" ); $error ( "length of string longer than the available storage" );
else else
begin begin
this.clear(); this.clear();
this.id = id; this.id = id;
end end
endfunction // set endfunction // set
function string get ( ); function string get ( );
...@@ -189,17 +189,17 @@ class WrtdId; ...@@ -189,17 +189,17 @@ class WrtdId;
wrtd_data d; wrtd_data d;
d = new[`WRTD_ID_LEN / 4]; d = new[`WRTD_ID_LEN / 4];
for ( i = 0; i < `WRTD_ID_LEN / 4; i ++ ) for ( i = 0; i < `WRTD_ID_LEN / 4; i ++ )
d[i] = 0; d[i] = 0;
for ( i = 0; i < this.id.len(); i ++ ) for ( i = 0; i < this.id.len(); i ++ )
d[i/4] |= this.id[i] << ( 8 * ( i % 4 ) ); d[i/4] |= this.id[i] << ( 8 * ( i % 4 ) );
return d; return d;
endfunction // data_pack endfunction // data_pack
function void data_unpack ( wrtd_data data ); function void data_unpack ( wrtd_data data );
if ( data.size() > `WRTD_ID_LEN / 4 ) if ( data.size() > `WRTD_ID_LEN / 4 )
$error ( "length of data longer than the available storage" ); $error ( "length of data longer than the available storage" );
else else
this.id = { <<32 { { <<8 { data } } } }; this.id = { <<32 { { <<8 { data } } } };
endfunction // data_unpack endfunction // data_unpack
function int is_empty ( ); function int is_empty ( );
......
hdl/testbench/include/wrtd_driver.svh
View file @ 47a61400
...@@ -44,8 +44,8 @@ class WrtdDrv; ...@@ -44,8 +44,8 @@ class WrtdDrv;
protected WrtdRepCapCollection alarms; protected WrtdRepCapCollection alarms;
function new ( CBusAccessor acc, uint64_t base, function new ( CBusAccessor acc, uint64_t base,
vIMockTurtleIRQ irq, string name = "", vIMockTurtleIRQ irq, string name = "",
byte unsigned enable_logging = 1 ); byte unsigned enable_logging = 1 );
this.name = name; this.name = name;
...@@ -58,9 +58,9 @@ class WrtdDrv; ...@@ -58,9 +58,9 @@ class WrtdDrv;
task mdisplay ( string str ); task mdisplay ( string str );
string tmp; string tmp;
if (this.name == "") if (this.name == "")
tmp = $sformatf("<%t> %s", $realtime, str); tmp = $sformatf("<%t> %s", $realtime, str);
else else
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str); tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
$display (tmp); $display (tmp);
endtask // mdisplay endtask // mdisplay
...@@ -88,88 +88,88 @@ class WrtdDrv; ...@@ -88,88 +88,88 @@ class WrtdDrv;
this.roots = new[this.nbr_cpus]; this.roots = new[this.nbr_cpus];
for ( i = 0; i < this.nbr_cpus; i++ ) for ( i = 0; i < this.nbr_cpus; i++ )
begin begin
this.hmq_words[i] = this.hmq_words[i] =
`TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD( mt.rom.getHmqDimensions( i, 0 ) ); `TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD( mt.rom.getHmqDimensions( i, 0 ) );
mt.enable_hmqi_irq ( i, 0, 1 ); mt.enable_hmqi_irq ( i, 0, 1 );
mt.enable_console_irq ( i, 1 ); mt.enable_console_irq ( i, 1 );
mt.reset_core ( i, 0 ); mt.reset_core ( i, 0 );
end end
fork fork
begin begin
for ( i = 0; i < this.nbr_cpus; i++ ) for ( i = 0; i < this.nbr_cpus; i++ )
begin begin
// wait for ready notification from firmware // wait for ready notification from firmware
cpu_ready = 0; cpu_ready = 0;
while ( cpu_ready == 0 ) while ( cpu_ready == 0 )
begin begin
val = 0; val = 0;
if ( mt.pending_cpu_notifications ( i ) != 0 ) if ( mt.pending_cpu_notifications ( i ) != 0 )
begin begin
mt.get_single_cpu_notification ( i, val ); mt.get_single_cpu_notification ( i, val );
if ( val == TRTL_CPU_NOTIFY_MAIN ) if ( val == TRTL_CPU_NOTIFY_MAIN )
cpu_ready = 1; cpu_ready = 1;
end end
# 1us; # 1us;
end end
// retrieve address of root // retrieve address of root
msg_get_config ( i, data ); msg_get_config ( i, data );
this.roots[i].addr = data[0]; this.roots[i].addr = data[0];
// retrieve root // retrieve root
msg_readw ( i, this.roots[i].addr, `WRTD_ROOT_WORD_SIZE, data ); msg_readw ( i, this.roots[i].addr, `WRTD_ROOT_WORD_SIZE, data );
this.roots[i].fw_name = new(); this.roots[i].fw_name = new();
this.roots[i].fw_name.data_unpack(data[1:4]); this.roots[i].fw_name.data_unpack(data[1:4]);
this.roots[i].fw_id = data[5]; this.roots[i].fw_id = data[5];
this.roots[i].capabilities = ( data[6] & 'hff000000 ) >> 24; this.roots[i].capabilities = ( data[6] & 'hff000000 ) >> 24;
this.roots[i].nbr_rules = ( data[6] & 'h00ff0000 ) >> 16; this.roots[i].nbr_rules = ( data[6] & 'h00ff0000 ) >> 16;
this.roots[i].nbr_alarms = ( data[6] & 'h0000ff00 ) >> 8; this.roots[i].nbr_alarms = ( data[6] & 'h0000ff00 ) >> 8;
this.roots[i].nbr_devs = ( data[6] & 'h000000ff ) >> 0; this.roots[i].nbr_devs = ( data[6] & 'h000000ff ) >> 0;
for ( j = 0; j < 4; j++) for ( j = 0; j < 4; j++)
begin begin
this.roots[i].nbr_channels[j] = ( data[9] >> j*8 ) & 'hff; this.roots[i].nbr_channels[j] = ( data[9] >> j*8 ) & 'hff;
this.roots[i].channel_dir[j] = ( data[10] >> j*8 ) & 'hff; this.roots[i].channel_dir[j] = ( data[10] >> j*8 ) & 'hff;
end end
this.roots[i].rules_addr = data[11]; this.roots[i].rules_addr = data[11];
this.roots[i].alarms_addr = data[12]; this.roots[i].alarms_addr = data[12];
// init free rule slots // init free rule slots
this.free_rule_slots[i] = this.roots[i].nbr_rules; this.free_rule_slots[i] = this.roots[i].nbr_rules;
// turn on all logging if enabled // turn on all logging if enabled
if ( this.enable_logging ) if ( this.enable_logging )
msg_writew ( i, this.roots[i].addr + 32, 1, { data[8] | 32'hff } ); msg_writew ( i, this.roots[i].addr + 32, 1, { data[8] | 32'hff } );
mdisplay( $sformatf("CPU %0d: WRTD app '%s', id '0x%x'", i, mdisplay( $sformatf("CPU %0d: WRTD app '%s', id '0x%x'", i,
this.roots[i].fw_name.get(), this.roots[i].fw_name.get(),
this.roots[i].fw_id) ); this.roots[i].fw_id) );
end end
// initialise rules // initialise rules
this.rules = new ( this.name ); this.rules = new ( this.name );
for ( i = 0; i < this.nbr_cpus; i++ ) for ( i = 0; i < this.nbr_cpus; i++ )
for ( j = 0; j < this.roots[i].nbr_rules; j++ ) for ( j = 0; j < this.roots[i].nbr_rules; j++ )
begin begin
new_rule = new ( this.name ); new_rule = new ( this.name );
this.rules.collection.push_back ( new_rule ); this.rules.collection.push_back ( new_rule );
end end
// initialise alarms // initialise alarms
this.alarms = new ( this.name ); this.alarms = new ( this.name );
for ( i = 0; i < this.nbr_cpus; i++ ) for ( i = 0; i < this.nbr_cpus; i++ )
for ( j = 0; j < this.roots[i].nbr_alarms; j++ ) for ( j = 0; j < this.roots[i].nbr_alarms; j++ )
begin begin
new_alarm = new ( this.name ); new_alarm = new ( this.name );
this.alarms.collection.push_back ( new_alarm ); this.alarms.collection.push_back ( new_alarm );
end end
end end
begin begin
while ( i != this.nbr_cpus ) while ( i != this.nbr_cpus )
begin begin
mt.update ( ); mt.update ( );
# 1us; # 1us;
end end
end end
join join
this.ready = 1; this.ready = 1;
...@@ -182,7 +182,7 @@ class WrtdDrv; ...@@ -182,7 +182,7 @@ class WrtdDrv;
MQueueMsg msg; MQueueMsg msg;
if ( data.size() < `WRTD_CFG_MSG_WORD_SIZE ) if ( data.size() < `WRTD_CFG_MSG_WORD_SIZE )
data = new[`WRTD_CFG_MSG_WORD_SIZE]; data = new[`WRTD_CFG_MSG_WORD_SIZE];
msg = new ( core, 0 ); msg = new ( core, 0 );
msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC; msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC;
...@@ -192,53 +192,53 @@ class WrtdDrv; ...@@ -192,53 +192,53 @@ class WrtdDrv;
while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us; while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us;
mt.hmq_receive_message ( msg ); mt.hmq_receive_message ( msg );
if ( msg.header.len != `WRTD_CFG_MSG_WORD_SIZE ) if ( msg.header.len != `WRTD_CFG_MSG_WORD_SIZE )
begin begin
$error ( "get_config: unexpected message header length" ); $error ( "get_config: unexpected message header length" );
mdisplay ( $sformatf ( "message received: %s", msg.tostring() ) ); mdisplay ( $sformatf ( "message received: %s", msg.tostring() ) );
end end
for ( i = 0; i < `WRTD_CFG_MSG_WORD_SIZE; i++ ) for ( i = 0; i < `WRTD_CFG_MSG_WORD_SIZE; i++ )
data[i] = msg.data[i]; data[i] = msg.data[i];
endtask // msg_get_config endtask // msg_get_config
task msg_readw ( int core, uint32_t addr, task msg_readw ( int core, uint32_t addr,
uint32_t count, ref uint32_t data[] ); uint32_t count, ref uint32_t data[] );
int i; int i;
MQueueMsg msg; MQueueMsg msg;
uint32_t tlen, offset; uint32_t tlen, offset;
if ( data.size() < count ) if ( data.size() < count )
data = new[count]; data = new[count];
offset = 0; offset = 0;
while ( offset < count ) while ( offset < count )
begin begin
tlen = this.hmq_words[core] - `WRTD_IO_MSG_WORD_SIZE; tlen = this.hmq_words[core] - `WRTD_IO_MSG_WORD_SIZE;
if ( tlen > count - offset ) if ( tlen > count - offset )
tlen = count - offset; tlen = count - offset;
msg = new ( core, 0 ); msg = new ( core, 0 );
msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC; msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC;
msg.header.msg_id = WRTD_ACTION_READW; msg.header.msg_id = WRTD_ACTION_READW;
msg.header.len = `WRTD_IO_MSG_WORD_SIZE; msg.header.len = `WRTD_IO_MSG_WORD_SIZE;
msg.data = '{ addr + offset, tlen }; msg.data = '{ addr + offset, tlen };
mt.hmq_send_message ( msg ); mt.hmq_send_message ( msg );
while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us; while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us;
mt.hmq_receive_message ( msg ); mt.hmq_receive_message ( msg );
if ( msg.header.len != tlen ) if ( msg.header.len != tlen )
begin begin
$error ( "readw: unexpected message header length" ); $error ( "readw: unexpected message header length" );
mdisplay ( $sformatf ( "message received: %s", msg.tostring() ) ); mdisplay ( $sformatf ( "message received: %s", msg.tostring() ) );
end end
for ( i = 0; i < tlen; i++ ) for ( i = 0; i < tlen; i++ )
data[offset+i] = msg.data[i]; data[offset+i] = msg.data[i];
offset += tlen; offset += tlen;
end end
endtask // msg_readw endtask // msg_readw
task msg_writew ( int core, uint32_t addr, task msg_writew ( int core, uint32_t addr,
uint32_t count, uint32_t data[] ); uint32_t count, uint32_t data[] );
int i; int i;
MQueueMsg msg; MQueueMsg msg;
uint32_t tlen, offset; uint32_t tlen, offset;
...@@ -246,22 +246,22 @@ class WrtdDrv; ...@@ -246,22 +246,22 @@ class WrtdDrv;
offset = 0; offset = 0;
while ( offset < count ) while ( offset < count )
begin begin
tlen = this.hmq_words[core] - `WRTD_IO_MSG_WORD_SIZE; tlen = this.hmq_words[core] - `WRTD_IO_MSG_WORD_SIZE;
if ( tlen > count - offset ) if ( tlen > count - offset )
tlen = count - offset; tlen = count - offset;
msg = new ( core, 0 ); msg = new ( core, 0 );
msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC; msg.header.flags = `TRTL_HMQ_HEADER_FLAG_RPC | `TRTL_HMQ_HEADER_FLAG_SYNC;
msg.header.msg_id = WRTD_ACTION_WRITEW; msg.header.msg_id = WRTD_ACTION_WRITEW;
msg.header.len = `WRTD_IO_MSG_WORD_SIZE + count; msg.header.len = `WRTD_IO_MSG_WORD_SIZE + count;
msg.data = '{ addr + offset, tlen }; msg.data = '{ addr + offset, tlen };
for ( i = 0; i < tlen; i++ ) for ( i = 0; i < tlen; i++ )
msg.data[i+2] = data[offset+i]; msg.data[i+2] = data[offset+i];
mt.hmq_send_message ( msg ); mt.hmq_send_message ( msg );
while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us; while ( mt.hmq_pending_messages ( msg.core, 0 ) == 0 ) #1us;
mt.hmq_receive_message ( msg ); mt.hmq_receive_message ( msg );
offset += tlen; offset += tlen;
end end
endtask // msg_writew endtask // msg_writew
...@@ -281,8 +281,8 @@ class WrtdDrv; ...@@ -281,8 +281,8 @@ class WrtdDrv;
endtask // remove_rule endtask // remove_rule
task set_rule ( string rep_cap_id, task set_rule ( string rep_cap_id,
string src, string dst, string src, string dst,
uint32_t delay_ns ); uint32_t delay_ns );
int idx; int idx;
WrtdRule rule; WrtdRule rule;
...@@ -290,10 +290,10 @@ class WrtdDrv; ...@@ -290,10 +290,10 @@ class WrtdDrv;
idx = this.rules.find ( rep_cap_id ); idx = this.rules.find ( rep_cap_id );
if ( idx == -1 ) if ( idx == -1 )
$error ( "%s repeated capability ID cannot be set because it does not exist", rep_cap_id ); $error ( "%s repeated capability ID cannot be set because it does not exist", rep_cap_id );
if ( this.rules.collection[idx].is_enabled ( ) ) if ( this.rules.collection[idx].is_enabled ( ) )
$error ( "%s repeated capability ID cannot be set because it is enabled", rep_cap_id ); $error ( "%s repeated capability ID cannot be set because it is enabled", rep_cap_id );
$cast ( rule, this.rules.collection[idx] ); $cast ( rule, this.rules.collection[idx] );
...@@ -310,7 +310,7 @@ class WrtdDrv; ...@@ -310,7 +310,7 @@ class WrtdDrv;
WrtdRule rule; WrtdRule rule;
if ( idx < 0 ) if ( idx < 0 )
$error ( "cannot write rule with negative index" ); $error ( "cannot write rule with negative index" );
$cast ( rule, this.rules.collection[idx] ); $cast ( rule, this.rules.collection[idx] );
...@@ -322,7 +322,7 @@ class WrtdDrv; ...@@ -322,7 +322,7 @@ class WrtdDrv;
endtask // write_rule endtask // write_rule
function void map_local_channel_to_cpu ( string ch_id, int ch_dir, function void map_local_channel_to_cpu ( string ch_id, int ch_dir,
ref int core, ref int ch_idx ); ref int core, ref int ch_idx );
int i, j, k, idx_in, idx_out, dev_dir; int i, j, k, idx_in, idx_out, dev_dir;
string dev_id; string dev_id;
...@@ -334,23 +334,23 @@ class WrtdDrv; ...@@ -334,23 +334,23 @@ class WrtdDrv;
ch_idx = -1; ch_idx = -1;
for ( i = 0; i < this.nbr_cpus; i++ ) for ( i = 0; i < this.nbr_cpus; i++ )
for ( j = 0; j < this.roots[i].nbr_devs; j++ ) for ( j = 0; j < this.roots[i].nbr_devs; j++ )
begin begin
dev_dir = this.roots[i].channel_dir[j]; dev_dir = this.roots[i].channel_dir[j];
for ( k = 0; k < this.roots[i].nbr_channels[j]; k++ ) for ( k = 0; k < this.roots[i].nbr_channels[j]; k++ )
begin begin
if ( dev_dir == WRTD_DIR_INPUT ) if ( dev_dir == WRTD_DIR_INPUT )
dev_id = $sformatf ( "LC-I%0d", idx_in++ ); dev_id = $sformatf ( "LC-I%0d", idx_in++ );
else else
dev_id = $sformatf ( "LC-O%0d", idx_out++ ); dev_id = $sformatf ( "LC-O%0d", idx_out++ );
if ( ( dev_dir == ch_dir ) && ( dev_id == ch_id ) ) if ( ( dev_dir == ch_dir ) && ( dev_id == ch_id ) )
begin begin
core = i; core = i;
ch_idx = k; ch_idx = k;
return; return;
end end
end end
end end
endfunction // map_local_channel_to_cpu endfunction // map_local_channel_to_cpu
...@@ -364,7 +364,7 @@ class WrtdDrv; ...@@ -364,7 +364,7 @@ class WrtdDrv;
idx = this.rules.find ( rep_cap_id ); idx = this.rules.find ( rep_cap_id );
if ( idx == -1 ) if ( idx == -1 )
$error ( "%s repeated capability ID cannot be enabled because it does not exist", rep_cap_id ); $error ( "%s repeated capability ID cannot be enabled because it does not exist", rep_cap_id );
$cast ( rule, this.rules.collection[idx] ); $cast ( rule, this.rules.collection[idx] );
...@@ -378,42 +378,42 @@ class WrtdDrv; ...@@ -378,42 +378,42 @@ class WrtdDrv;
map_local_channel_to_cpu ( rule.get_dst(), WRTD_DIR_OUTPUT, dst_cpu, dst_ch ); map_local_channel_to_cpu ( rule.get_dst(), WRTD_DIR_OUTPUT, dst_cpu, dst_ch );
if ( dst_cpu >= 0 ) // local output device if ( dst_cpu >= 0 ) // local output device
begin begin
/* If source is network message and this cpu can receive from /* If source is network message and this cpu can receive from
network, set cpu affinity to this cpu */ network, set cpu affinity to this cpu */
if ( ( src_cpu == -1 ) && ( this.roots[dst_cpu].capabilities & `WRTD_CAP_NET_RX ) ) if ( ( src_cpu == -1 ) && ( this.roots[dst_cpu].capabilities & `WRTD_CAP_NET_RX ) )
src_cpu = dst_cpu; src_cpu = dst_cpu;
/* Otherwise find the first cpu that is capable of net RX */ /* Otherwise find the first cpu that is capable of net RX */
else else
for ( src_cpu = 0; src_cpu < this.nbr_cpus; src_cpu++ ) for ( src_cpu = 0; src_cpu < this.nbr_cpus; src_cpu++ )
if ( this.roots[src_cpu].capabilities & `WRTD_CAP_NET_RX ) if ( this.roots[src_cpu].capabilities & `WRTD_CAP_NET_RX )
break; break;
end end
else // network destination else // network destination
begin begin
dst_ch = `WRTD_DEST_CH_NET; dst_ch = `WRTD_DEST_CH_NET;
/* If source cpu can also send to /* If source cpu can also send to
network, set dest cpu affinity to that cpu */ network, set dest cpu affinity to that cpu */
if ( ( src_cpu >= 0 ) && ( this.roots[src_cpu].capabilities & `WRTD_CAP_NET_TX ) ) if ( ( src_cpu >= 0 ) && ( this.roots[src_cpu].capabilities & `WRTD_CAP_NET_TX ) )
dst_cpu = src_cpu; dst_cpu = src_cpu;
/* Otherwise find the first cpu that is capable of net TX */ /* Otherwise find the first cpu that is capable of net TX */
else else
for ( dst_cpu = 0; dst_cpu < this.nbr_cpus; dst_cpu++ ) for ( dst_cpu = 0; dst_cpu < this.nbr_cpus; dst_cpu++ )
if ( this.roots[dst_cpu].capabilities & `WRTD_CAP_NET_TX ) if ( this.roots[dst_cpu].capabilities & `WRTD_CAP_NET_TX )
break; break;
end end
// TODO: handle network to network events // TODO: handle network to network events
if ( ( src_cpu < 0 ) || ( dst_cpu < 0 ) || if ( ( src_cpu < 0 ) || ( dst_cpu < 0 ) ||
( src_cpu >= this.nbr_cpus ) || ( dst_cpu >= this.nbr_cpus ) ) ( src_cpu >= this.nbr_cpus ) || ( dst_cpu >= this.nbr_cpus ) )
$error ( "cannot determine source and/or destination cpu for rule" ); $error ( "cannot determine source and/or destination cpu for rule" );
/* If the same CPU can handle both input and output, use special value so that /* If the same CPU can handle both input and output, use special value so that
the firmware will know not to forward this event to another CPU (it does not the firmware will know not to forward this event to another CPU (it does not
know its own index) */ know its own index) */
if ( src_cpu == dst_cpu ) if ( src_cpu == dst_cpu )
dst_cpu = `WRTD_DEST_CPU_LOCAL; dst_cpu = `WRTD_DEST_CPU_LOCAL;
// TODO: handle free_rule_slots per cpu // TODO: handle free_rule_slots per cpu
...@@ -449,7 +449,7 @@ class WrtdDrv; ...@@ -449,7 +449,7 @@ class WrtdDrv;
uint32_t data[]; uint32_t data[];
if ( idx < 0 ) if ( idx < 0 )
$error ( "cannot write alarm with negative index" ); $error ( "cannot write alarm with negative index" );
core = this.alarms.collection[idx].get_core ( ); core = this.alarms.collection[idx].get_core ( );
//index = this.alarms.collection[idx].get_index (); //index = this.alarms.collection[idx].get_index ();
...@@ -474,10 +474,10 @@ class WrtdDrv; ...@@ -474,10 +474,10 @@ class WrtdDrv;
ret = ""; ret = "";
if ( msg.header.msg_id != `WRTD_ACTION_LOG ) if ( msg.header.msg_id != `WRTD_ACTION_LOG )
begin begin
$error ( "log_msg_tostring: unknown message id %.8x", msg.header.msg_id ); $error ( "log_msg_tostring: unknown message id %.8x", msg.header.msg_id );
return ret; return ret;
end end
msg_tstamp = new (); msg_tstamp = new ();
msg_tstamp.data_unpack ( msg.data[11:13] ); msg_tstamp.data_unpack ( msg.data[11:13] );
...@@ -497,29 +497,29 @@ class WrtdDrv; ...@@ -497,29 +497,29 @@ class WrtdDrv;
case ( msg_type ) case ( msg_type )
WRTD_LOG_MSG_EV_GENERATED : WRTD_LOG_MSG_EV_GENERATED :
begin begin
$cast ( gen_reason, msg.data[1] ); $cast ( gen_reason, msg.data[1] );
ret = { ret, $sformatf ( ", reason: %s", gen_reason.name() ) }; ret = { ret, $sformatf ( ", reason: %s", gen_reason.name() ) };
end end
WRTD_LOG_MSG_EV_CONSUMED : WRTD_LOG_MSG_EV_CONSUMED :
begin begin
$cast ( con_reason, msg.data[1] ); $cast ( con_reason, msg.data[1] );
ret = { ret, $sformatf ( ", reason: %s", con_reason.name() ) }; ret = { ret, $sformatf ( ", reason: %s", con_reason.name() ) };
end end
WRTD_LOG_MSG_EV_DISCARDED : WRTD_LOG_MSG_EV_DISCARDED :
begin begin
$cast ( dsc_reason, msg.data[1] ); $cast ( dsc_reason, msg.data[1] );
ret = { ret, $sformatf ( ", reason: %s", dsc_reason.name() ) }; ret = { ret, $sformatf ( ", reason: %s", dsc_reason.name() ) };
end end
WRTD_LOG_MSG_EV_NETWORK : WRTD_LOG_MSG_EV_NETWORK :
begin begin
$cast ( net_reason, msg.data[1] ); $cast ( net_reason, msg.data[1] );
ret = { ret, $sformatf ( ", reason: %s", net_reason.name() ) }; ret = { ret, $sformatf ( ", reason: %s", net_reason.name() ) };
end end
endcase; // case ( msg_type ) endcase; // case ( msg_type )
...@@ -532,22 +532,22 @@ class WrtdDrv; ...@@ -532,22 +532,22 @@ class WrtdDrv;
MQueueMsg msg; MQueueMsg msg;
for (int i = 0; i < this.nbr_cpus; i++) for (int i = 0; i < this.nbr_cpus; i++)
begin begin
while ( mt.hmq_pending_messages ( i, 0 ) ) while ( mt.hmq_pending_messages ( i, 0 ) )
begin begin
msg = new ( i, 0 ); msg = new ( i, 0 );
mt.hmq_peek_message ( msg ); mt.hmq_peek_message ( msg );
if ( msg.header.msg_id != `WRTD_ACTION_LOG ) break; if ( msg.header.msg_id != `WRTD_ACTION_LOG ) break;
mt.hmq_receive_message ( msg ); mt.hmq_receive_message ( msg );
mdisplay ( $sformatf ( "LOG MSG from core %0d: %s", i, log_msg_tostring ( msg ) ) ); mdisplay ( $sformatf ( "LOG MSG from core %0d: %s", i, log_msg_tostring ( msg ) ) );
end end
end end
endtask // check_logs endtask // check_logs
task update ( ); task update ( );
mt.update ( ); mt.update ( );
if ( this.enable_logging ) if ( this.enable_logging )
check_logs ( ); check_logs ( );
endtask // update endtask // update
endclass // WrtdDrv endclass // WrtdDrv
......
hdl/testbench/include/wrtd_rep_cap.svh
View file @ 47a61400
...@@ -47,9 +47,9 @@ virtual class WrtdRepCap; ...@@ -47,9 +47,9 @@ virtual class WrtdRepCap;
task mdisplay ( string str ); task mdisplay ( string str );
string tmp; string tmp;
if (this.name == "") if (this.name == "")
tmp = $sformatf("<%t> %s", $realtime, str); tmp = $sformatf("<%t> %s", $realtime, str);
else else
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str); tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
$display (tmp); $display (tmp);
endtask // mdisplay endtask // mdisplay
...@@ -83,9 +83,9 @@ virtual class WrtdRepCap; ...@@ -83,9 +83,9 @@ virtual class WrtdRepCap;
function void set_enable ( int enable ); function void set_enable ( int enable );
if ( enable > 0) if ( enable > 0)
this.enabled = 1; this.enabled = 1;
else else
this.enabled = 0; this.enabled = 0;
endfunction // set_enable endfunction // set_enable
function void set_disable ( ); function void set_disable ( );
...@@ -110,17 +110,17 @@ class WrtdRepCapCollection; ...@@ -110,17 +110,17 @@ class WrtdRepCapCollection;
task mdisplay ( string str ); task mdisplay ( string str );
string tmp; string tmp;
if (this.name == "") if (this.name == "")
tmp = $sformatf("<%t> %s", $realtime, str); tmp = $sformatf("<%t> %s", $realtime, str);
else else
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str); tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
$display (tmp); $display (tmp);
endtask // mdisplay endtask // mdisplay
function void validate_id ( string rep_cap_id ); function void validate_id ( string rep_cap_id );
if ( rep_cap_id.len() > `WRTD_ID_LEN ) if ( rep_cap_id.len() > `WRTD_ID_LEN )
$error ( "repeated capability name '%s' is too long", rep_cap_id ); $error ( "repeated capability name '%s' is too long", rep_cap_id );
if ( rep_cap_id.len() == 0 ) if ( rep_cap_id.len() == 0 )
$error ( "repeated capability name is null" ); $error ( "repeated capability name is null" );
endfunction // validate_id endfunction // validate_id
function int add ( string rep_cap_id ); function int add ( string rep_cap_id );
...@@ -131,21 +131,21 @@ class WrtdRepCapCollection; ...@@ -131,21 +131,21 @@ class WrtdRepCapCollection;
idx = -1; idx = -1;
for ( i = 0; i < this.collection.size(); i++ ) for ( i = 0; i < this.collection.size(); i++ )
begin begin
if ( this.collection[i].match ( rep_cap_id ) ) if ( this.collection[i].match ( rep_cap_id ) )
begin begin
$error ( "'%s' repeated capability ID already exists", rep_cap_id ); $error ( "'%s' repeated capability ID already exists", rep_cap_id );
return -1; return -1;
end end
if ( idx == -1 && this.collection[i].is_free() ) if ( idx == -1 && this.collection[i].is_free() )
idx = i; idx = i;
end end
if ( idx == -1 ) if ( idx == -1 )
$error ( "cannot add '%s' repeated capability, no space available", rep_cap_id ); $error ( "cannot add '%s' repeated capability, no space available", rep_cap_id );
else else
this.collection[idx].set_rep_cap_id ( rep_cap_id ); this.collection[idx].set_rep_cap_id ( rep_cap_id );
return idx; return idx;
endfunction // add endfunction // add
...@@ -156,8 +156,8 @@ class WrtdRepCapCollection; ...@@ -156,8 +156,8 @@ class WrtdRepCapCollection;
validate_id ( rep_cap_id ); validate_id ( rep_cap_id );
for ( i = 0; i < this.collection.size(); i++ ) for ( i = 0; i < this.collection.size(); i++ )
if ( this.collection[i].match ( rep_cap_id ) ) if ( this.collection[i].match ( rep_cap_id ) )
return i; return i;
return -1; return -1;
endfunction // find endfunction // find
...@@ -168,15 +168,15 @@ class WrtdRepCapCollection; ...@@ -168,15 +168,15 @@ class WrtdRepCapCollection;
idx = find ( rep_cap_id ); idx = find ( rep_cap_id );
if ( idx == -1 ) if ( idx == -1 )
begin begin
$error ( "%s repeated capability ID cannot be removed because it does not exist", rep_cap_id ); $error ( "%s repeated capability ID cannot be removed because it does not exist", rep_cap_id );
return idx; return idx;
end end
if ( this.collection[idx].is_enabled ( ) ) if ( this.collection[idx].is_enabled ( ) )
$error ( "%s repeated capability ID cannot be removed because it is enabled", rep_cap_id ); $error ( "%s repeated capability ID cannot be removed because it is enabled", rep_cap_id );
else else
this.collection[idx].clear(); this.collection[idx].clear();
return idx; return idx;
endfunction // remove endfunction // remove
......
hdl/testbench/include/wrtd_rule.svh
View file @ 47a61400
...@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap; ...@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap;
protected uint32_t hold_off_ns; protected uint32_t hold_off_ns;
protected uint32_t resync_period_ns; protected uint32_t resync_period_ns;
protected uint32_t resync_factor; protected uint32_t resync_factor;
int hash_chain; int hash_chain;
protected uint32_t rx_events; protected uint32_t rx_events;
protected WrtdTstamp rx_last; protected WrtdTstamp rx_last;
protected uint32_t tx_events; protected uint32_t tx_events;
......
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 47a61400
...@@ -226,14 +226,14 @@ module dut_env ...@@ -226,14 +226,14 @@ module dut_env
gc_sfp_i2c_adapter gc_sfp_i2c_adapter
SFP_I2C SFP_I2C
( (
.clk_i (clk_125m_pll), .clk_i (clk_125m_pll),
.rst_n_i (1'b1), .rst_n_i (1'b1),
.scl_i (sfp_scl), .scl_i (sfp_scl),
.sda_i (sfp_sda), .sda_i (sfp_sda),
.sda_en_o (sfp_sda_en), .sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1), .sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF) .sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
); );
assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz; assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz;
...@@ -243,66 +243,66 @@ module dut_env ...@@ -243,66 +243,66 @@ module dut_env
always@(negedge clk_400m_adc) always@(negedge clk_400m_adc)
begin begin
#625ps; #625ps;
if(adc_div == 1) begin if(adc_div == 1) begin
adc0_fr <= ~adc0_fr; adc0_fr <= ~adc0_fr;
adc_div <= 0; adc_div <= 0;
end end
else begin else begin
adc_div <= adc_div + 1; adc_div <= adc_div + 1;
end end
end end
always@(posedge adc0_fr) always@(posedge adc0_fr)
begin begin
if ((adc0_data > 400) || (adc0_data < -400)) begin if ((adc0_data > 400) || (adc0_data < -400)) begin
adc_data_dir = ~adc_data_dir; adc_data_dir = ~adc_data_dir;
end end
if (adc_data_dir == 0) begin if (adc_data_dir == 0) begin
adc0_data = adc0_data + 8; adc0_data = adc0_data + 8;
end end
else begin else begin
adc0_data = adc0_data - 8; adc0_data = adc0_data - 8;
end end
adc0_dat_odd = {4{adc0_data[13]}}; adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}}; adc0_dat_even = {4{adc0_data[12]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[11]}}; adc0_dat_odd = {4{adc0_data[11]}};
adc0_dat_even = {4{adc0_data[10]}}; adc0_dat_even = {4{adc0_data[10]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[9]}}; adc0_dat_odd = {4{adc0_data[9]}};
adc0_dat_even = {4{adc0_data[8]}}; adc0_dat_even = {4{adc0_data[8]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[7]}}; adc0_dat_odd = {4{adc0_data[7]}};
adc0_dat_even = {4{adc0_data[6]}}; adc0_dat_even = {4{adc0_data[6]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[5]}}; adc0_dat_odd = {4{adc0_data[5]}};
adc0_dat_even = {4{adc0_data[4]}}; adc0_dat_even = {4{adc0_data[4]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[3]}}; adc0_dat_odd = {4{adc0_data[3]}};
adc0_dat_even = {4{adc0_data[2]}}; adc0_dat_even = {4{adc0_data[2]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{adc0_data[1]}}; adc0_dat_odd = {4{adc0_data[1]}};
adc0_dat_even = {4{adc0_data[0]}}; adc0_dat_even = {4{adc0_data[0]}};
#1250ps; #1250ps;
adc0_dat_odd = {4{1'b0}}; adc0_dat_odd = {4{1'b0}};
adc0_dat_even = {4{1'b0}}; adc0_dat_even = {4{1'b0}};
end end
initial begin initial begin
// Skip WR SoftPLL lock // Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111; WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0; multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0; multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0; multiplier.D3.OPMODE_dly = 0;
end // initial begin end // initial begin
endmodule // dut_env endmodule // dut_env
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ 47a61400
...@@ -63,74 +63,74 @@ module main; ...@@ -63,74 +63,74 @@ module main;
wait ((hostA.ready == 1'b1) && (hostB.ready == 1'b1)); wait ((hostA.ready == 1'b1) && (hostB.ready == 1'b1));
fork fork
begin begin
accA = hostA.get_accessor(); accA = hostA.get_accessor();
accA.set_default_xfer_size(4); accA.set_default_xfer_size(4);
devA = new (accA, MT_BASE, MtIrqMonitorA, "DUT:A"); devA = new (accA, MT_BASE, MtIrqMonitorA, "DUT:A");
devA.init(); devA.init();
devA.add_rule ( "rule0" ); devA.add_rule ( "rule0" );
devA.set_rule ( "rule0", "LC-I5", "NET0", 0 ); devA.set_rule ( "rule0", "LC-I5", "NET0", 0 );
devA.enable_rule ( "rule0" ); devA.enable_rule ( "rule0" );
// Config DUTA to trigger on external trigger and get 64 samples // Config DUTA to trigger on external trigger and get 64 samples
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET); val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET); val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val); accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39; expected = 'h39;
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected) if (val != expected)
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected); $fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:A] <%t> ADC configured and armed", $realtime); $display ("[DUT:A] <%t> ADC configured and armed", $realtime);
wait (duta_acq_state == 1); wait (duta_acq_state == 1);
end end
begin begin
accB = hostB.get_accessor(); accB = hostB.get_accessor();
accB.set_default_xfer_size(4); accB.set_default_xfer_size(4);
devB = new (accB, MT_BASE, MtIrqMonitorB, "DUT:B"); devB = new (accB, MT_BASE, MtIrqMonitorB, "DUT:B");
devB.init(); devB.init();
devB.add_rule ( "rule0" ); devB.add_rule ( "rule0" );
devB.set_rule ( "rule0", "NET0", "LC-O1", 50000 ); devB.set_rule ( "rule0", "NET0", "LC-O1", 50000 );
devB.enable_rule ( "rule0" ); devB.enable_rule ( "rule0" );
// Config DUTB to trigger on WRTD and get 64 samples // Config DUTB to trigger on WRTD and get 64 samples
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET); val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val); accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39; expected = 'h39;
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected) if (val != expected)
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected); $fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:B] <%t> ADC configured and armed", $realtime); $display ("[DUT:B] <%t> ADC configured and armed", $realtime);
wait (dutb_acq_state == 1); wait (dutb_acq_state == 1);
end end
join join
#50us; #50us;
...@@ -146,57 +146,57 @@ module main; ...@@ -146,57 +146,57 @@ module main;
duta_ext_trig <= 1'b0; duta_ext_trig <= 1'b0;
fork fork
begin begin
wait (duta_acq_state == 1); wait (duta_acq_state == 1);
$display("[DUT:A] <%t> END ACQ 1", $realtime); $display("[DUT:A] <%t> END ACQ 1", $realtime);
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val); accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:A] <%t> TRIG POSITION %.8x", $realtime, val); $display("[DUT:A] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer // DMA transfer
accA.write('h2008, val); // dma start addr accA.write('h2008, val); // dma start addr
accA.write('h200C, 'h00001000); // host addr accA.write('h200C, 'h00001000); // host addr
accA.write('h2010, 'h00000000); accA.write('h2010, 'h00000000);
accA.write('h2014, 'h00000100); // len << 2 accA.write('h2014, 'h00000100); // len << 2
accA.write('h2018, 'h00000000); // next accA.write('h2018, 'h00000000); // next
accA.write('h201C, 'h00000000); accA.write('h201C, 'h00000000);
accA.write('h2020, 'h00000000); // attrib: pcie -> host accA.write('h2020, 'h00000000); // attrib: pcie -> host
accA.write('h2000, 'h00000001); // xfer start accA.write('h2000, 'h00000001); // xfer start
wait (DUTA.DUT.dma_irq[0] == 1); wait (DUTA.DUT.dma_irq[0] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime); $display("[DUT:A] <%t> END DMA 1", $realtime);
end end
begin begin
wait (dutb_acq_state == 1); wait (dutb_acq_state == 1);
$display("[DUT:B] <%t> END ACQ 1", $realtime); $display("[DUT:B] <%t> END ACQ 1", $realtime);
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val); accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:B] <%t> TRIG POSITION %.8x", $realtime, val); $display("[DUT:B] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer // DMA transfer
accB.write('h2008, val); // dma start addr accB.write('h2008, val); // dma start addr
accB.write('h200C, 'h00001000); // host addr accB.write('h200C, 'h00001000); // host addr
accB.write('h2010, 'h00000000); accB.write('h2010, 'h00000000);
accB.write('h2014, 'h00000100); // len << 2 accB.write('h2014, 'h00000100); // len << 2
accB.write('h2018, 'h00000000); // next accB.write('h2018, 'h00000000); // next
accB.write('h201C, 'h00000000); accB.write('h201C, 'h00000000);
accB.write('h2020, 'h00000000); // attrib: pcie -> host accB.write('h2020, 'h00000000); // attrib: pcie -> host
accB.write('h2000, 'h00000001); // xfer start accB.write('h2000, 'h00000001); // xfer start
wait (DUTB.DUT.dma_irq[0] == 1); wait (DUTB.DUT.dma_irq[0] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime); $display("[DUT:B] <%t> END DMA 1", $realtime);
end end
join join
...@@ -205,11 +205,11 @@ module main; ...@@ -205,11 +205,11 @@ module main;
initial begin initial begin
forever begin forever begin
if ( ( devA != null ) && ( devA.ready ) ) if ( ( devA != null ) && ( devA.ready ) )
devA.update(); devA.update();
if ( ( devB != null ) && ( devB.ready ) ) if ( ( devB != null ) && ( devB.ready ) )
devB.update(); devB.update();
#1us; #1us;
end end
end end
......
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @ 47a61400
...@@ -41,8 +41,8 @@ module simple_tdc_driver ...@@ -41,8 +41,8 @@ module simple_tdc_driver
); );
typedef struct { typedef struct {
int channel; int channel;
time ts; time ts;
} acam_fifo_entry; } acam_fifo_entry;
acam_fifo_entry pulses[$]; acam_fifo_entry pulses[$];
...@@ -71,30 +71,30 @@ module simple_tdc_driver ...@@ -71,30 +71,30 @@ module simple_tdc_driver
time now; time now;
wait (pulses.size() != 0) wait (pulses.size() != 0)
; ;
t = pulses.pop_front(); t = pulses.pop_front();
now = $time; now = $time;
if (t.ts <= now) if (t.ts <= now)
$display("[DUT] <%t> TDC: pulse in the past (%t now=%t)!", $realtime, t.ts, now); $display("[DUT] <%t> TDC: pulse in the past (%t now=%t)!", $realtime, t.ts, now);
else else
begin begin
const int fifo_n = t.channel / 4; const int fifo_n = t.channel / 4;
logic [27:0] val; logic [27:0] val;
#(t.ts - now) ; #(t.ts - now) ;
val[27:26] = t.channel & 2'b11; val[27:26] = t.channel & 2'b11;
val[25:18] = start; val[25:18] = start;
val[17] = 1'b1; val[17] = 1'b1;
val[16:0] = (t.ts - start_time) / 81ps; val[16:0] = (t.ts - start_time) / 81ps;
$display("[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)", $display("[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)",
$realtime, t.ts, t.channel, start, val[16:0], start_time); $realtime, t.ts, t.channel, start, val[16:0], start_time);
fifos[t.channel / 4].push_back(val); fifos[t.channel / 4].push_back(val);
end end
end end
initial begin initial begin
...@@ -110,34 +110,34 @@ module simple_tdc_driver ...@@ -110,34 +110,34 @@ module simple_tdc_driver
always@(posedge clk) begin always@(posedge clk) begin
start_rep++; start_rep++;
if (start_rep == start_timer) begin if (start_rep == start_timer) begin
start_rep = 0; start_rep = 0;
if (restart_pulse) begin if (restart_pulse) begin
start = 1; start = 1;
restart_pulse = 0; restart_pulse = 0;
start01 = ($time - restart_time) / 81ps; start01 = ($time - restart_time) / 81ps;
end end
else begin else begin
start_time = $time; start_time = $time;
start++; start++;
end end
end end
end end
always@(rd) begin always@(rd) begin
rdata <= 28'bz; rdata <= 28'bz;
if (rd == 1'b0) begin if (rd == 1'b0) begin
if (addr == 8) begin if (addr == 8) begin
rdata <= fifos[0].pop_front(); rdata <= fifos[0].pop_front();
end end
else if (addr == 9) begin else if (addr == 9) begin
rdata <= fifos[1].pop_front(); rdata <= fifos[1].pop_front();
end end
else if (addr == 10) begin else if (addr == 10) begin
rdata <= start01; rdata <= start01;
end end
else begin else begin
$display("[DUT] <%t> invalid ACAM read 0x%x", $realtime, addr); $display("[DUT] <%t> invalid ACAM read 0x%x", $realtime, addr);
end end
end end
end end
...@@ -160,8 +160,8 @@ module simple_fdelay_mon ...@@ -160,8 +160,8 @@ module simple_fdelay_mon
); );
typedef struct { typedef struct {
int channel; int channel;
time ts; time ts;
} fifo_entry; } fifo_entry;
fifo_entry pulses[$]; fifo_entry pulses[$];
...@@ -180,28 +180,28 @@ module simple_fdelay_mon ...@@ -180,28 +180,28 @@ module simple_fdelay_mon
prev = 0; prev = 0;
while (pulses.size() != 0) begin while (pulses.size() != 0) begin
@pulse ; @pulse ;
now = $time; now = $time;
$display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", now, len, val, pulse); $display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", now, len, val, pulse);
for(int i = 0; i < 4; i++) begin for(int i = 0; i < 4; i++) begin
if (prev[i] == 1'b0 && pulse[i] == 1'b1) begin if (prev[i] == 1'b0 && pulse[i] == 1'b1) begin
automatic fifo_entry e = pulses.pop_front(); automatic fifo_entry e = pulses.pop_front();
automatic time diff; automatic time diff;
$display("[FDEL] pulse on channel %0d", i); $display("[FDEL] pulse on channel %0d", i);
if (e.channel != i) begin if (e.channel != i) begin
$display("FAIL: [FDEL] Bad channel (expected %0d)", e.channel); $display("FAIL: [FDEL] Bad channel (expected %0d)", e.channel);
$finish(1); $finish(1);
end end
diff = now - e.ts; diff = now - e.ts;
if (diff > 2us && diff < -2us) begin if (diff > 2us && diff < -2us) begin
$display("FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t", now, e.ts); $display("FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t", now, e.ts);
$finish(1); $finish(1);
end end
end end
end end
prev = pulse; prev = pulse;
end end
$display("SUCCESS: done"); $display("SUCCESS: done");
$finish(0); $finish(0);
...@@ -213,7 +213,7 @@ module dut_env ...@@ -213,7 +213,7 @@ module dut_env
( (
IVHDWishboneMaster host, IVHDWishboneMaster host,
output clk_sys, rst_sys_n, output clk_sys, rst_sys_n,
sfp_txp_o, sfp_txn_o, sfp_txp_o, sfp_txn_o,
input sfp_rxp_i, sfp_rxn_i input sfp_rxp_i, sfp_rxn_i
); );
...@@ -310,16 +310,16 @@ module dut_env ...@@ -310,16 +310,16 @@ module dut_env
simple_tdc_driver simple_tdc_driver
TDC TDC
( (
.clk(clk_31m5_acam), .clk(clk_31m5_acam),
.addr(tdc_addr), .addr(tdc_addr),
.data(tdc_data), .data(tdc_data),
.wr(tdc_wr_n), .wr(tdc_wr_n),
.rd(tdc_rd_n), .rd(tdc_rd_n),
.ef1(tdc_ef1), .ef1(tdc_ef1),
.ef2(tdc_ef2), .ef2(tdc_ef2),
.tstart(tdc_start), .tstart(tdc_start),
.intflag(tdc_int) .intflag(tdc_int)
); );
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Fine Delay monitor // Fine Delay monitor
...@@ -328,10 +328,10 @@ module dut_env ...@@ -328,10 +328,10 @@ module dut_env
simple_fdelay_mon simple_fdelay_mon
FDL FDL
( (
.len (fdl_len), .len (fdl_len),
.val (fdl_val), .val (fdl_val),
.pulse (fdl_pulse) .pulse (fdl_pulse)
); );
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
...@@ -341,14 +341,14 @@ module dut_env ...@@ -341,14 +341,14 @@ module dut_env
gc_sfp_i2c_adapter gc_sfp_i2c_adapter
SFP_I2C SFP_I2C
( (
.clk_i (clk_125m_pll), .clk_i (clk_125m_pll),
.rst_n_i (1'b1), .rst_n_i (1'b1),
.scl_i (sfp_scl), .scl_i (sfp_scl),
.sda_i (sfp_sda), .sda_i (sfp_sda),
.sda_en_o (sfp_sda_en), .sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1), .sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF) .sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
); );
assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz; assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz;
...@@ -377,17 +377,17 @@ module dut_env ...@@ -377,17 +377,17 @@ module dut_env
initial begin initial begin
// Skip WR SoftPLL lock // Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111; WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0; multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0; multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core. force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0; multiplier.D3.OPMODE_dly = 0;
end // initial begin end // initial begin
endmodule // dut_env endmodule // dut_env
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @ 47a61400
...@@ -92,9 +92,9 @@ module main; ...@@ -92,9 +92,9 @@ module main;
initial begin initial begin
forever begin forever begin
if ( ( dev != null ) && ( dev.ready ) ) if ( ( dev != null ) && ( dev.ready ) )
dev.update (); dev.update ();
#1us; #1us;
end end
end end
......
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