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White Rabbit Trigger Distribution
Commit 6f60e0c7 authored by Tristan Gingold's avatar Tristan Gingold
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Renaming to fmc-adc-100m14b4cha-svec

parent fdc151d8
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builder/fmc-adc-100m14b4cha-svec/config.yaml 0 → 100644
View file @ 6f60e0c7
repo:
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
bus:
input:
"wb_adc{n}_trigin_slave"
output:
"wb_adc{n}_trigout_slave"
builder/fmc-adc-100m14b4cha-svec/repo.txt 0 → 100644
View file @ 6f60e0c7
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
builder/fmc-adc-100m14b4cha-svec/svec-fmc0.ucf 0 → 100644
View file @ 6f60e0c7
# DDR0 (bank 4)
NET "ddr0_rzq_b" LOC = L7;
NET "ddr0_we_n_o" LOC = F4;
NET "ddr0_udqs_p_b" LOC = K2;
NET "ddr0_udqs_n_b" LOC = K1;
NET "ddr0_udm_o" LOC = K4;
NET "ddr0_reset_n_o" LOC = G5;
NET "ddr0_ras_n_o" LOC = C1;
NET "ddr0_odt_o" LOC = E4;
NET "ddr0_ldqs_p_b" LOC = J5;
NET "ddr0_ldqs_n_b" LOC = J4;
NET "ddr0_ldm_o" LOC = K3;
NET "ddr0_cke_o" LOC = C4;
NET "ddr0_ck_p_o" LOC = E3;
NET "ddr0_ck_n_o" LOC = E1;
NET "ddr0_cas_n_o" LOC = B1;
NET "ddr0_dq_b[15]" LOC = M1;
NET "ddr0_dq_b[14]" LOC = M2;
NET "ddr0_dq_b[13]" LOC = L1;
NET "ddr0_dq_b[12]" LOC = L3;
NET "ddr0_dq_b[11]" LOC = L4;
NET "ddr0_dq_b[10]" LOC = L5;
NET "ddr0_dq_b[9]" LOC = M3;
NET "ddr0_dq_b[8]" LOC = M4;
NET "ddr0_dq_b[7]" LOC = H1;
NET "ddr0_dq_b[6]" LOC = H2;
NET "ddr0_dq_b[5]" LOC = G1;
NET "ddr0_dq_b[4]" LOC = G3;
NET "ddr0_dq_b[3]" LOC = J1;
NET "ddr0_dq_b[2]" LOC = J3;
NET "ddr0_dq_b[1]" LOC = H3;
NET "ddr0_dq_b[0]" LOC = H4;
NET "ddr0_ba_o[2]" LOC = F3;
NET "ddr0_ba_o[1]" LOC = D1;
NET "ddr0_ba_o[0]" LOC = D2;
NET "ddr0_a_o[13]" LOC = B5;
NET "ddr0_a_o[12]" LOC = A4;
NET "ddr0_a_o[11]" LOC = G4;
NET "ddr0_a_o[10]" LOC = D5;
NET "ddr0_a_o[9]" LOC = A2;
NET "ddr0_a_o[8]" LOC = B2;
NET "ddr0_a_o[7]" LOC = B3;
NET "ddr0_a_o[6]" LOC = F1;
NET "ddr0_a_o[5]" LOC = F2;
NET "ddr0_a_o[4]" LOC = C5;
NET "ddr0_a_o[3]" LOC = E5;
NET "ddr0_a_o[2]" LOC = A3;
NET "ddr0_a_o[1]" LOC = D3;
NET "ddr0_a_o[0]" LOC = D4;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
# FMC0
NET "fmc0_adc_ext_trigger_n_i" LOC = "A15";
NET "fmc0_adc_ext_trigger_p_i" LOC = "B15";
NET "fmc0_adc_dco_n_i" LOC = "A16";
NET "fmc0_adc_dco_p_i" LOC = "C16";
NET "fmc0_adc_fr_n_i" LOC = "G21";
NET "fmc0_adc_fr_p_i" LOC = "H21";
NET "fmc0_adc_outa_n_i[0]" LOC = "E17";
NET "fmc0_adc_outa_p_i[0]" LOC = "F17";
NET "fmc0_adc_outb_n_i[0]" LOC = "G16";
NET "fmc0_adc_outb_p_i[0]" LOC = "H16";
NET "fmc0_adc_outa_n_i[1]" LOC = "E19";
NET "fmc0_adc_outa_p_i[1]" LOC = "F19";
NET "fmc0_adc_outb_n_i[1]" LOC = "F18";
NET "fmc0_adc_outb_p_i[1]" LOC = "G18";
NET "fmc0_adc_outa_n_i[2]" LOC = "K21";
NET "fmc0_adc_outa_p_i[2]" LOC = "L21";
NET "fmc0_adc_outb_n_i[2]" LOC = "L20";
NET "fmc0_adc_outb_p_i[2]" LOC = "M20";
NET "fmc0_adc_outa_n_i[3]" LOC = "F22";
NET "fmc0_adc_outa_p_i[3]" LOC = "G22";
NET "fmc0_adc_outb_n_i[3]" LOC = "L19";
NET "fmc0_adc_outb_p_i[3]" LOC = "M19";
NET "fmc0_adc_spi_din_i" LOC = "F11";
NET "fmc0_adc_spi_dout_o" LOC = "K11";
NET "fmc0_adc_spi_sck_o" LOC = "L11";
NET "fmc0_adc_spi_cs_adc_n_o" LOC = "J13";
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = "H11";
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = "G11";
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = "J12";
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = "H12";
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = "H13";
NET "fmc0_adc_gpio_led_acq_o" LOC = "K12";
NET "fmc0_adc_gpio_led_trig_o" LOC = "L12";
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "fmc0_adc_gpio_si570_oe_o" LOC = "A25";
NET "fmc0_adc_si570_scl_b" LOC = "H14";
NET "fmc0_adc_si570_sda_b" LOC = "J14";
NET "fmc0_adc_one_wire_b" LOC = "E9";
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "rst_ddr_333m_n" TPTHRU = ddr0_rst;
TIMESPEC TS_ddr0_rst_tig = FROM FFS THRU ddr0_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "cmp_ddr0_ctrl_bank/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank4_clk;
TIMEGRP "ddr0_clk" = "ddr_clk_333m" "ddr_bank4_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_reg = FROM ddr0_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
builder/fmc-adc-100m14b4cha-svec/svec-fmc1.ucf 0 → 100644
View file @ 6f60e0c7
# DDR1 (bank 5)
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
NET "ddr_udqs_n_b[1]" LOC = K30;
NET "ddr_udm_o[1]" LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]" LOC = K26;
NET "ddr_odt_o[1]" LOC = E30;
NET "ddr_ldqs_p_b[1]" LOC = J29;
NET "ddr_ldqs_n_b[1]" LOC = J30;
NET "ddr_ldm_o[1]" LOC = J28;
NET "ddr_cke_o[1]" LOC = B29;
NET "ddr_ck_p_o[1]" LOC = E27;
NET "ddr_ck_n_o[1]" LOC = E28;
NET "ddr_cas_n_o[1]" LOC = K27;
NET "ddr_dq_b[31]" LOC = M30;
NET "ddr_dq_b[30]" LOC = M28;
NET "ddr_dq_b[29]" LOC = M27;
NET "ddr_dq_b[28]" LOC = M26;
NET "ddr_dq_b[27]" LOC = L30;
NET "ddr_dq_b[26]" LOC = L29;
NET "ddr_dq_b[25]" LOC = L28;
NET "ddr_dq_b[24]" LOC = L27;
NET "ddr_dq_b[23]" LOC = F30;
NET "ddr_dq_b[22]" LOC = F28;
NET "ddr_dq_b[21]" LOC = G28;
NET "ddr_dq_b[20]" LOC = G27;
NET "ddr_dq_b[19]" LOC = G30;
NET "ddr_dq_b[18]" LOC = G29;
NET "ddr_dq_b[17]" LOC = H30;
NET "ddr_dq_b[16]" LOC = H28;
NET "ddr_ba_o[5]" LOC = D26;
NET "ddr_ba_o[4]" LOC = C27;
NET "ddr_ba_o[3]" LOC = D27;
NET "ddr_a_o[27]" LOC = A28;
NET "ddr_a_o[26]" LOC = B30;
NET "ddr_a_o[25]" LOC = A26;
NET "ddr_a_o[24]" LOC = F26;
NET "ddr_a_o[23]" LOC = A27;
NET "ddr_a_o[22]" LOC = B27;
NET "ddr_a_o[21]" LOC = C29;
NET "ddr_a_o[20]" LOC = H27;
NET "ddr_a_o[19]" LOC = H26;
NET "ddr_a_o[18]" LOC = F27;
NET "ddr_a_o[17]" LOC = E29;
NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
builder/fmc-adc-100m14b4cha-svec/top.vhd 0 → 100644
View file @ 6f60e0c7
[use]
use work.fmc_adc_mezzanine_pkg.all;
use work.ddr3_ctrl_pkg.all;
[ports]
------------------------------------------
-- DDR (banks 4 for fmc0 and 5 for fmc1)
------------------------------------------
ddr{n}_a_o : out std_logic_vector(13 downto 0);
ddr{n}_ba_o : out std_logic_vector(2 downto 0);
ddr{n}_cas_n_o : out std_logic;
ddr{n}_ck_n_o : out std_logic;
ddr{n}_ck_p_o : out std_logic;
ddr{n}_cke_o : out std_logic;
ddr{n}_dq_b : inout std_logic_vector(15 downto 0);
ddr{n}_ldm_o : out std_logic;
ddr{n}_ldqs_n_b : inout std_logic;
ddr{n}_ldqs_p_b : inout std_logic;
ddr{n}_odt_o : out std_logic;
ddr{n}_ras_n_o : out std_logic;
ddr{n}_reset_n_o : out std_logic;
ddr{n}_rzq_b : inout std_logic;
ddr{n}_udm_o : out std_logic;
ddr{n}_udqs_n_b : inout std_logic;
ddr{n}_udqs_p_b : inout std_logic;
ddr{n}_we_n_o : out std_logic;
------------------------------------------
-- FMC slots
------------------------------------------
fmc{n}_adc_ext_trigger_p_i : in std_logic; -- External trigger
fmc{n}_adc_ext_trigger_n_i : in std_logic;
fmc{n}_adc_dco_p_i : in std_logic; -- ADC data clock
fmc{n}_adc_dco_n_i : in std_logic;
fmc{n}_adc_fr_p_i : in std_logic; -- ADC frame start
fmc{n}_adc_fr_n_i : in std_logic;
fmc{n}_adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
fmc{n}_adc_outa_n_i : in std_logic_vector(3 downto 0);
fmc{n}_adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
fmc{n}_adc_outb_n_i : in std_logic_vector(3 downto 0);
fmc{n}_adc_spi_din_i : in std_logic; -- SPI data from FMC
fmc{n}_adc_spi_dout_o : out std_logic; -- SPI data to FMC
fmc{n}_adc_spi_sck_o : out std_logic; -- SPI clock
fmc{n}_adc_spi_cs_adc_n_o : out std_logic; -- SPI ADC chip select (active low)
fmc{n}_adc_spi_cs_dac1_n_o : out std_logic; -- SPI channel 1 offset DAC chip select (active low)
fmc{n}_adc_spi_cs_dac2_n_o : out std_logic; -- SPI channel 2 offset DAC chip select (active low)
fmc{n}_adc_spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low)
fmc{n}_adc_spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low)
fmc{n}_adc_gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
fmc{n}_adc_gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
fmc{n}_adc_gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
fmc{n}_adc_gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
fmc{n}_adc_gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
fmc{n}_adc_gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
fmc{n}_adc_gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
fmc{n}_adc_gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
fmc{n}_adc_si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
fmc{n}_adc_si570_sda_b : inout std_logic; -- I2C bus data (Si570)
fmc{n}_adc_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
[sdb-decl]
constant c_FMC{n}_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WB_DDR{n}_DAT_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006610",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Data-Access ")));
constant c_WB_DDR{n}_ADR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000003",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"10006611",
version => x"00000001",
date => x"20130704",
name => "WB-DDR-Addr-Access ")));
[sdb-layout]
c_WB_SLAVE_FMC{n}_ADC => f_sdb_embed_bridge(c_FMC{n}_BRIDGE_SDB, x"{addr}" or x"2000"),
c_WB_SLAVE_FMC{n}_DDR_ADR => f_sdb_embed_device(c_WB_DDR{n}_ADR_SDB, x"{addr}" or x"4000"),
c_WB_SLAVE_FMC{n}_DDR_DAT => f_sdb_embed_device(c_WB_DDR{n}_DAT_SDB, x"{addr}" or x"5000"),
[decls]
constant g_FMC{n}_MULTISHOT_RAM_SIZE : natural := 2048;
constant g_FMC{n}_CALIB_SOFT_IP : string := "TRUE";
-- Wishbone bus from cross-clocking module to FMC{n} mezzanine
signal cnx_fmc{n}_sync_master_out : t_wishbone_master_out;
signal cnx_fmc{n}_sync_master_in : t_wishbone_master_in;
-- Wishbone bus from MT cpus to adc.
signal wb_adc{n}_trigin_slave_out : t_wishbone_slave_out;
signal wb_adc{n}_trigin_slave_in : t_wishbone_slave_in;
signal wb_adc{n}_trigout_slave_out : t_wishbone_slave_out;
signal wb_adc{n}_trigout_slave_in : t_wishbone_slave_in;
-- Wishbone buses from FMC ADC cores to DDR controller
signal fmc{n}_wb_ddr_in : t_wishbone_master_data64_in;
signal fmc{n}_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal ddr{n}_wr_fifo_empty : std_logic;
signal ddr{n}_wr_fifo_empty_sync : std_logic;
signal fmc{n}_irq : std_logic;
signal tm_time_valid_sync : std_logic;
function f_ddr{n}_bank_sel return string is
begin
if {n} = 0 then
return "SVEC_BANK4_64B_32B";
else
return "SVEC_BANK5_64B_32B";
end if;
end function f_ddr{n}_bank_sel;
-- Conversion of g_simulation to string needed for DDR controller
function fmc{n}_f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_FMC{n}_SIMULATION_STR : string :=
fmc{n}_f_int2string(g_SIMULATION);
-- DDR
signal ddr{n}_status : std_logic_vector(31 downto 0);
signal ddr{n}_calib_done : std_logic;
signal ddr{n}_addr_cnt : unsigned(31 downto 0);
signal ddr{n}_dat_cyc_d : std_logic;
signal ddr{n}_addr_cnt_en : std_logic;
[body]
cmp_fmc{n}_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc{n}_irq,
synced_o => fmc_host_irq({n}));
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
-- Mezzanine system managment I2C master
-- Mezzanine SPI master
-- Mezzanine I2C
-- ADC core
-- Mezzanine 1-wire master
------------------------------------------------------------------------------
cmp{n}_xwb_clock_bridge : xwb_clock_bridge
port map (
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_ADC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC{n}_ADC),
master_clk_i => clk_ref_125m,
master_rst_n_i => rst_ref_125m_n,
master_i => cnx_fmc{n}_sync_master_in,
master_o => cnx_fmc{n}_sync_master_out);
cmp{n}_fmc_ddr_wr_fifo_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => ddr{n}_wr_fifo_empty,
synced_o => ddr{n}_wr_fifo_empty_sync);
cmp{n}_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp{n}_fmc_adc_mezzanine : entity work.fmc_adc_mezzanine
generic map (
g_MULTISHOT_RAM_SIZE => g_FMC{n}_MULTISHOT_RAM_SIZE,
g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE)
port map (
sys_clk_i => clk_ref_125m,
sys_rst_n_i => rst_ref_125m_n,
wb_csr_slave_i => cnx_fmc{n}_sync_master_out,
wb_csr_slave_o => cnx_fmc{n}_sync_master_in,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_rst_n_i => rst_ref_125m_n,
wb_ddr_master_i => fmc{n}_wb_ddr_in,
wb_ddr_master_o => fmc{n}_wb_ddr_out,
ddr_wr_fifo_empty_i => ddr{n}_wr_fifo_empty_sync,
trig_irq_o => open,
acq_end_irq_o => open,
eic_irq_o => fmc{n}_irq,
acq_cfg_ok_o => open,
wb_trigin_slave_i => wb_adc{n}_trigin_slave_in,
wb_trigin_slave_o => wb_adc{n}_trigin_slave_out,
wb_trigout_slave_i => wb_adc{n}_trigout_slave_in,
wb_trigout_slave_o => wb_adc{n}_trigout_slave_out,
ext_trigger_p_i => fmc{n}_adc_ext_trigger_p_i,
ext_trigger_n_i => fmc{n}_adc_ext_trigger_n_i,
adc_dco_p_i => fmc{n}_adc_dco_p_i,
adc_dco_n_i => fmc{n}_adc_dco_n_i,
adc_fr_p_i => fmc{n}_adc_fr_p_i,
adc_fr_n_i => fmc{n}_adc_fr_n_i,
adc_outa_p_i => fmc{n}_adc_outa_p_i,
adc_outa_n_i => fmc{n}_adc_outa_n_i,
adc_outb_p_i => fmc{n}_adc_outb_p_i,
adc_outb_n_i => fmc{n}_adc_outb_n_i,
gpio_dac_clr_n_o => fmc{n}_adc_gpio_dac_clr_n_o,
gpio_led_acq_o => fmc{n}_adc_gpio_led_acq_o,
gpio_led_trig_o => fmc{n}_adc_gpio_led_trig_o,
gpio_ssr_ch1_o => fmc{n}_adc_gpio_ssr_ch1_o,
gpio_ssr_ch2_o => fmc{n}_adc_gpio_ssr_ch2_o,
gpio_ssr_ch3_o => fmc{n}_adc_gpio_ssr_ch3_o,
gpio_ssr_ch4_o => fmc{n}_adc_gpio_ssr_ch4_o,
gpio_si570_oe_o => fmc{n}_adc_gpio_si570_oe_o,
spi_din_i => fmc{n}_adc_spi_din_i,
spi_dout_o => fmc{n}_adc_spi_dout_o,
spi_sck_o => fmc{n}_adc_spi_sck_o,
spi_cs_adc_n_o => fmc{n}_adc_spi_cs_adc_n_o,
spi_cs_dac1_n_o => fmc{n}_adc_spi_cs_dac1_n_o,
spi_cs_dac2_n_o => fmc{n}_adc_spi_cs_dac2_n_o,
spi_cs_dac3_n_o => fmc{n}_adc_spi_cs_dac3_n_o,
spi_cs_dac4_n_o => fmc{n}_adc_spi_cs_dac4_n_o,
si570_scl_b => fmc{n}_adc_si570_scl_b,
si570_sda_b => fmc{n}_adc_si570_sda_b,
mezz_one_wire_b => fmc{n}_adc_one_wire_b,
sys_scl_b => fmc{n}_scl_b,
sys_sda_b => fmc{n}_sda_b,
wr_tm_link_up_i => tm_link_up,
wr_tm_time_valid_i => tm_time_valid_sync,
wr_tm_tai_i => tm_tai,
wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en);
------------------------------------------------------------------------------
-- DDR controllers for adc{n}
------------------------------------------------------------------------------
cmp_ddr{n}_ctrl_bank : ddr3_ctrl
generic map (
g_RST_ACT_LOW => 1, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => f_ddr{n}_bank_sel,
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_FMC{n}_SIMULATION_STR,
g_CALIB_SOFT_IP => g_FMC{n}_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => rst_ddr_333m_n,
status_o => ddr{n}_status,
ddr3_dq_b => ddr{n}_dq_b,
ddr3_a_o => ddr{n}_a_o,
ddr3_ba_o => ddr{n}_ba_o,
ddr3_ras_n_o => ddr{n}_ras_n_o,
ddr3_cas_n_o => ddr{n}_cas_n_o,
ddr3_we_n_o => ddr{n}_we_n_o,
ddr3_odt_o => ddr{n}_odt_o,
ddr3_rst_n_o => ddr{n}_reset_n_o,
ddr3_cke_o => ddr{n}_cke_o,
ddr3_dm_o => ddr{n}_ldm_o,
ddr3_udm_o => ddr{n}_udm_o,
ddr3_dqs_p_b => ddr{n}_ldqs_p_b,
ddr3_dqs_n_b => ddr{n}_ldqs_n_b,
ddr3_udqs_p_b => ddr{n}_udqs_p_b,
ddr3_udqs_n_b => ddr{n}_udqs_n_b,
ddr3_clk_p_o => ddr{n}_ck_p_o,
ddr3_clk_n_o => ddr{n}_ck_n_o,
ddr3_rzq_b => ddr{n}_rzq_b,
wb0_rst_n_i => rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc{n}_wb_ddr_out.sel,
wb0_cyc_i => fmc{n}_wb_ddr_out.cyc,
wb0_stb_i => fmc{n}_wb_ddr_out.stb,
wb0_we_i => fmc{n}_wb_ddr_out.we,
wb0_addr_i => fmc{n}_wb_ddr_out.adr,
wb0_data_i => fmc{n}_wb_ddr_out.dat,
wb0_data_o => fmc{n}_wb_ddr_in.dat,
wb0_ack_o => fmc{n}_wb_ddr_in.ack,
wb0_stall_o => fmc{n}_wb_ddr_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr{n}_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).sel,
wb1_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).cyc,
wb1_stb_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).stb,
wb1_we_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).we,
wb1_data_i => cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).dat,
wb1_addr_i => std_logic_vector(ddr{n}_addr_cnt),
wb1_data_o => cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_DAT).dat,
wb1_ack_o => cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_DAT).ack,
wb1_stall_o => cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_DAT).stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open);
fmc{n}_wb_ddr_in.err <= '0';
fmc{n}_wb_ddr_in.rty <= '0';
ddr{n}_calib_done <= ddr{n}_status(0);
-- DDR address counter
-- The address counter is set by writing to the c_WB_SLAVE_FMC_DDR_ADR wb peripheral.
-- Then the counter is incremented on every access to the c_WB_SLAVE_FMC_DDR_DAT wb peripheral.
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1
p_ddr{n}_dat_cyc : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr{n}_dat_cyc_d <= '0';
else
ddr{n}_dat_cyc_d <= cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).cyc;
end if;
end if;
end process p_ddr{n}_dat_cyc;
ddr{n}_addr_cnt_en <= not(cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_DAT).cyc) and ddr{n}_dat_cyc_d;
-- address counter
p_ddr{n}_addr_cnt : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr{n}_addr_cnt <= (others => '0');
elsif (cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).we = '1' and
cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).cyc = '1') then
ddr{n}_addr_cnt <= unsigned(cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).dat);
elsif (ddr{n}_addr_cnt_en = '1') then
ddr{n}_addr_cnt <= ddr{n}_addr_cnt + 1;
end if;
end if;
end process p_ddr{n}_addr_cnt;
-- ack generation
p_ddr{n}_addr_ack : process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).ack <= '0';
elsif (cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).stb = '1' and
cnx_slave_in(c_WB_SLAVE_FMC{n}_DDR_ADR).cyc = '1') then
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).ack <= '1';
else
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).ack <= '0';
end if;
end if;
end process p_ddr{n}_addr_ack;
-- Address counter read back
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).dat <= std_logic_vector(ddr{n}_addr_cnt);
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_DAT).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_DAT).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC{n}_DDR_ADR).stall <= '0';
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