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White Rabbit Trigger Distribution
Commit 7533c4d0 authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'origin/proposed_master' into develop

parents 0c081bed 7cb88275
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.gitmodules
View file @ 7533c4d0
......@@ -28,3 +28,9 @@
[submodule "dependencies/gn4124-core"]
path = dependencies/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "dependencies/spec"]
path = dependencies/spec
url = https://ohwr.org/project/spec.git
[submodule "dependencies/svec"]
path = dependencies/svec
url = https://ohwr.org/project/svec.git
ddr3-sp6-core @ 1a129390
Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
fmc-adc-100m14b4cha-gw @ ce4ef303
Subproject commit 1e0e561f4902940a0b3ec85bdc863ac92cc650da
Subproject commit ce4ef303e38b0119c5c62a5634f8426ddc69b068
general-cores @ 284373b7
Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
Subproject commit 284373b7ea1db559dd323634dd34a8dba1811c12
gn4124-core @ 91d5efac
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
mock-turtle @ add8319c
Subproject commit b07df87ad36d963beb7d7596b3dffa4221d6bd58
Subproject commit add8319c68770cd2dac9c10842aad8487aeb1717
spec @ 1b48d764
Subproject commit 1b48d76430920f62e871ce0e46bc61731f04d9b1
svec @ 3da89c5c
Subproject commit 3da89c5c700260ce0d7296438d463d789c44161d
vme64x-core @ 366ca4db
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
doc/basic_concepts.rst
View file @ 7533c4d0
......@@ -104,6 +104,9 @@ as information regarding any discarded :ref:`event`, along with the reason for d
The Event Log has a limited storage buffer. Newer entries will overwrite older, unread ones.
For an explanation of the fields of an Event Log entry, please refer to the documentation of the
:cpp:func:`wrtd_get_next_event_log_entry` function.
.. _local_channel:
Local Channel
......
doc/installation.rst
View file @ 7533c4d0
......@@ -11,8 +11,3 @@ Installation
Permissions
===========
.. _node_id:
Node Identification
===================
doc/usage_clib.rst
View file @ 7533c4d0
......@@ -98,15 +98,27 @@ The initialisation API provides the functions to initiate/close a connection to
well as to reset it.
:cpp:func:`wrtd_init` is the first function that should be called by any program, in order to obtain
the "device token" to be used in all subsequent function calls. See also :ref:`node_id` on how to
figure out the ``resource_name`` of a :ref:`node`.
the "device token" to be used in all subsequent function calls.
Conversely, :cpp:func:`wrtd_close` should be called before exiting the program. No further WRTD
library functions can be used after that.
In order to identify the :ref:`node` to connect to, it is necessary to provide the ID of that
:ref:`node`. This ID is simply an integer that uniquely identifies a Node within a given host
system. Functions :cpp:func:`wrtd_get_node_count` and :cpp:func:`wrtd_get_node_id` can help you
figure out the ID of each :ref:`node`.
.. important::
The Node ID is not sequential, nor does it start counting from zero (or one). It might well be
that you only have one Node in a given host, and that it has an ID different than 1. Always
retrieve therefore the Node ID with :cpp:func:`wrtd_get_node_id`.
.. doxygenfunction:: wrtd_init
.. doxygenfunction:: wrtd_close
.. doxygenfunction:: wrtd_reset
.. doxygenfunction:: wrtd_get_node_count
.. doxygenfunction:: wrtd_get_node_id
.. code-block:: c
:caption: Opening and closing a connection to a Node.
......@@ -115,8 +127,17 @@ library functions can be used after that.
int main(void) {
wrtd_dev *wrtd;
wrtd_status status;
uint32_t node_count;
uint32_t node_id;
status = wrtd_init("MT01", false, NULL, &wrtd);
/* Not really used in this example */
status = wrtd_get_node_count(&node_count);
/* Get the ID of the first Node */
status= wrtd_get_node_id(1, &node_id);
/* Access the first Node */
status = wrtd_init(node_id, false, NULL, &wrtd);
/* This will erase all defined rules and alarms
from the Node, so it might not be what you want
......
doc/usage_pywrap.rst
View file @ 7533c4d0
......@@ -16,61 +16,51 @@ The wrapper is provided as a Python package with a single class that encapsulate
All the provided class methods have exactly the same names (and function) as their C counterparts,
without the "wrtd\_" prefix.
To start using it, simply import the PyWrtd package and instantiate a :py:class:`PyWrtd` object,
passing to it the :ref:`identifier of the Node<node_id>` you wish to access.
If the identifier is wrong or if the user does not have the correct permissions to access it, WRTD
will return :cpp:enumerator:`WRTD_ERROR_RESOURCE_UNKNOWN`.
.. code-block:: python
.. hint::
>>> from PyWrtd import PyWrtd
>>> wrtd = PyWrtd("bad id")
Error 0xbffa0060: WRTD_ERROR_RESOURCE_UNKNOWN
>>> wrtd = PyWrtd("MT01")
>>> wrtd
<PyWrtd.PyWrtd object at 0x7fa9aeeaee48>
Compared to the :ref:`clib`, the Python wrapper lacks the :cpp:func:`wrtd_init`,
:cpp:func:`wrtd_close`, :cpp:func:`wrtd_get_error` and :cpp:func:`wrtd_error_message` functions,
because the Python wrapper performs these tasks (initialisation and error handling) internally.
.. hint::
The provided :ref:`tools <tools>` are built on top of this Python wrapper, so they also serve as
a good example of how to use the wrapper.
Error Handling API
------------------
.. automethod:: PyWrtd.get_error
.. code-block:: python
>>> wrtd.get_error()
(0, 'WRTD_SUCCESS ')
.. automethod:: PyWrtd.error_message
.. code-block:: python
>>> wrtd.error_message(PyWrtd.WRTD_SUCCESS)
'WRTD_SUCCESS'
.. _pyapi_init:
Initialisation API
------------------
Compared to the :ref:`clib` :ref:`api_init`, the Python version lacks the :cpp:func:`wrtd_init` and
:cpp:func:`wrtd_close` functions, because the Python wrapper performs these tasks internally.
To start using it, simply import the PyWrtd package and instantiate a :py:class:`PyWrtd` object,
passing to it the ID of the Node you wish to access.
In order to retrieve the ID of the :ref:`node`, the :py:class:`PyWrtd` class provides the static
methods :py:meth:`PyWrtd.PyWrtd.get_node_count` and :py:meth:`PyWrtd.PyWrtd.get_node_id` that can be
used before you instantiate the :py:class:`PyWrtd` object.
If the ID is wrong or if the user does not have the correct :ref:`permissions <permissions>` to
access it, WRTD will return :cpp:enumerator:`WRTD_ERROR_RESOURCE_UNKNOWN`.
.. automethod:: PyWrtd.reset
.. code-block:: python
>>> from PyWrtd import PyWrtd
>>> wrtd = PyWrtd(11)
OSError: [Errno -1074134944] WRTD_ERROR_RESOURCE_UNKNOWN
>>> PyWrtd.get_node_id(3)
OSError: [Errno -1074134944] WRTD_ERROR_RESOURCE_UNKNOWN
>>> PyWrtd.get_node_count()
2
>>> PyWrtd.get_node_id(1)
10
>>> wrtd = PyWrtd(10)
>>> wrtd
<PyWrtd.PyWrtd object at 0x7fa9aeeaee48>
>>> wrtd.reset()
>>> wrtd.add_rule('rule1')
>>> # Query number of declared rules
>>> wrtd.get_attr_int32(PyWrtd.WRTD_GLOBAL_REP_CAP_ID, PyWrtd.WRTD_ATTR_RULE_COUNT)
1
>>> # After reset, 'rule1' should be gone
>>> wrtd.reset()
>>> wrtd.get_attr_int32(PyWrtd.WRTD_GLOBAL_REP_CAP_ID, PyWrtd.WRTD_ATTR_RULE_COUNT)
0
.. automethod:: PyWrtd.get_node_count
.. automethod:: PyWrtd.get_node_id
.. automethod:: PyWrtd.reset
.. _pyapi_attr:
......
doc/usage_tools.rst
View file @ 7533c4d0
......@@ -5,46 +5,43 @@ Tools
.. module:: PyWrtd
WRTD provides two comand-line, Python based tools for accessing a :ref:`node`. One
(:ref:`wrtd_config`) is used to add/remove/configure :ref:`Rules <rule>` and :ref:`Alarms <alarm>`,
and to display information about the :ref:`node` while the other (:ref:`wrtd_logging`) is used for
reading entries from the :ref:`event_log`.
WRTD provides a comand-line, Python based tool (:ref:`wrtd_tool`) for accessing a :ref:`node`.
Both tools have a built-in help system that can be accessed by passing the ``--help`` (or ``-h``)
option to the tool.
.. hint::
Both tools take an obligatory ``-D`` option to specify the :ref:`node` to access. For more details,
please refer to :ref:`node_id`. You also need to run them with the proper :ref:`permissions`.
Please make sure that you run the tool wih the proper :ref:`permissions <permissions>`.
For details on how to install these tools (and their dependencies), please refer to
For details on how to install the tool (and their dependencies), please refer to
:numref:`installation`.
.. _wrtd_config:
.. _wrtd_tool:
wrtd-config
-----------
wrtd-tool
---------
``wrtd-config`` is a command-line tool that implements several different operations on a
``wrtd-tool`` is a command-line tool that implements several different operations on a
:ref:`node`. It supports most of the functionality provided by the :ref:`pywrap`.
A list of the available commands can be retrieved by passing the ``-h`` option to the tool:
.. code-block:: console
> wrtd-config -h
usage: wrtd-config [-h] -D DEV <command> ...
> wrtd-tool -h
usage: wrtd-tool [-h] <command> ...
WRTD node configuration tool
WRTD Node configuration tool
optional arguments:
-h, --help show this help message and exit
-D DEV, --dev-id DEV MockTurtle device ID (integer) to open
Available commands:
<command> (Use "<command> -h" to get more details)
list-nodes List the IDs of all detected WRTD Nodes
sys-info Show system information
sys-time Show current system time
set-log Enable/Disable logging
enable-log Enable logging
disable-log Disable logging
show-log Show log entries
clear-log Clear pending log entries
list-rules List all defined Rules
add-rule Define a new Rule
......@@ -71,12 +68,14 @@ and passing the ``-h`` option after the command:
.. code-block:: console
> wrtd-config set-alarm -h
usage: wrtd-config set-alarm [-h] -d DELAY [-s SETUP] [-p PERIOD]
[-c COUNT] [-e] name
> wrtd-tool set-alarm -h
usage: wrtd-tool set-alarm [-h] -d DELAY [-s SETUP] [-p PERIOD]
[-c COUNT] [-e] <node_id> <alarm_id>
positional arguments:
name The name of the Alarm to configure
<node_id> The ID of the WRTD Node (int, can be hex with "0x"
prefix)
<alarm_id> The ID of the Alarm (string up to 15 characters)
optional arguments:
-h, --help show this help message and exit
......@@ -100,36 +99,58 @@ and passing the ``-h`` option after the command:
-e, --enable Also enable the Alarm after configuring it.
If a command returns an :ref:`Error Code <api_error_codes>`, the underlying :ref:`pywrap` will raise
an OSError exception and will provide all the available details coming from
:py:meth:`PyWrtd.get_error`:
an OSError exception and will provide all the available details:
.. code-block:: console
> wrtd-config -D 1 remove-alarm alarm5
OSError: [Errno -1074122744] Error 0xbffa3008: WRTD_ERROR_ALARM_DOES_NOT_EXIST wrtd_remove_alarm/wrtd_find_alarm: The specified alarm has not been defined
> wrtd-tool remove-alarm 1 alarm5
OSError: [Errno -1074122744] WRTD_ERROR_ALARM_DOES_NOT_EXIST
wrtd_remove_alarm/wrtd_find_alarm: The specified alarm has not been defined
.. _wrtd_logging:
wrtd-logging
------------
wrtd-logging is a simple command-line tool that monitors the :ref:`event_log` of a :ref:`node`.
A list of the available options can be retrieved by passing the ``-h`` option to the tool:
Here's an example on how to configure a :ref:`rule` and check the :ref:`event_log` for :ref:`Events
<event>`:
.. code-block:: console
> wrtd-logging -h
usage: wrtd-logging [-h] -D DEV [-c COUNT]
WRTD node log monitoring tool
optional arguments:
-h, --help show this help message and exit
-D DEV, --dev-id DEV MockTurtle device ID (integer) to open
-c COUNT, --count COUNT
Number of entries to read (0 = infinite)
-e, --enable Enable event logging on the Node if not already
enabled.
Log entries are printed using the format presented in :cpp:func:`wrtd_get_next_event_log_entry`.
> wrtd-tool list-nodes
-> WRTD Node detected with ID: 10
> wrtd-tool list-rules 10
0 Rules defined.
> wrtd-tool add-rule 10 rule0
> wrtd-tool set-rule 10 rule0 LC-I1 NET0
> wrtd-tool list-rules 10 -v
1 Rule defined:
+ rule0
+ Configuration
- Name..............: rule0
- Source............: LC-I1
- Destination.......: NET0
- Enabled...........: False
- Send Late.........: True
- Repeat Count......: 0
- Delay.............: 0.000ns
- Holdoff...........: 0.000ns
- Resync Period.....: 0.000ns
- Resync Factor.....: 0
+ Statistics
- RX Events.........: 0
- Last RX...........: Never
- TX Events.........: 0
- Last TX...........: Never
- Latency (min).....: 0.000ns
- Latency (avg).....: 0.000ns
- Latency (max).....: 0.000ns
- Missed (late).....: 0
- Missed (holdoff)..: 0
- Missed (no sync)..: 0
- Missed (overflow).: 0
- Last Missed.......: Never
> wrtd-tool enable-rule 10 rule0
> wrtd-tool enable-log 10
> wrtd-tool show-log 10 -c 6
Id:LC-I1 |Seq:0000|...|...|GENERATED|DEVICE_0
Id:NET0 |Seq:0016|...|...|NETWORK |TX
Id:LC-I1 |Seq:0000|...|...|GENERATED|DEVICE_0
Id:NET0 |Seq:0017|...|...|TX
Id:LC-I1 |Seq:0000|...|...|GENERATED|DEVICE_0
Id:NET0 |Seq:0018|...|...|TX
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @ 7533c4d0
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "spec"
target = "xilinx"
action = "synthesis"
......@@ -14,21 +9,14 @@ syn_top = "wrtd_ref_spec150t_adc"
syn_project = "wrtd_ref_spec150t_adc.xise"
syn_tool = "ise"
fetchto = "../../../dependencies"
ctrls = ["bank3_64b_32b"]
syn_pre_project_cmd = "make -C ../../../software/firmware"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_spec150t_adc.ucf",
"buildinfo_pkg.vhd",
]
modules = {
......@@ -36,3 +24,17 @@ modules = {
"../../top/wrtd_ref_spec150t_adc",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_64b_32b"]
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 7533c4d0
......@@ -2,370 +2,6 @@
# IO Location Constraints
#===============================================================================
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_gpio_b[1]" LOC = U16;
NET "gn_gpio_b[0]" LOC = AB19;
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_?_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_rxn_i" LOC = C15;
NET "sfp_rxp_i" LOC = D15;
NET "sfp_txn_o" LOC = A16;
NET "sfp_txp_o" LOC = B16;
NET "sfp_los_i" LOC = D18;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll20dac_sync_n_o" LOC = B3;
NET "plldac_din_o" LOC = C4;
NET "plldac_sclk_o" LOC = A4;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AA3;
NET "spi_sclk_o" LOC = Y20;
NET "spi_mosi_o" LOC = AB20;
NET "spi_miso_i" LOC = AA20;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2;
NET "uart_rxd_i" LOC = A2;
NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_sfp_red_o" LOC = D5;
NET "led_sfp_green_o" LOC = E5;
NET "led_sfp_red_o" IOSTANDARD = "LVCMOS25";
NET "led_sfp_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# PCB Buttons and LEDs
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# GN4124
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_we_n_o" LOC = H2;
NET "ddr0_udqs_p_b" LOC = V2;
NET "ddr0_udqs_n_b" LOC = V1;
NET "ddr0_udm_o" LOC = P3;
NET "ddr0_reset_n_o" LOC = E3;
NET "ddr0_ras_n_o" LOC = M5;
NET "ddr0_odt_o" LOC = L6;
NET "ddr0_ldqs_p_b" LOC = N3;
NET "ddr0_ldqs_n_b" LOC = N1;
NET "ddr0_ldm_o" LOC = N4;
NET "ddr0_cke_o" LOC = F2;
NET "ddr0_ck_p_o" LOC = K4;
NET "ddr0_ck_n_o" LOC = K3;
NET "ddr0_cas_n_o" LOC = M4;
NET "ddr0_dq_b[15]" LOC = Y1;
NET "ddr0_dq_b[14]" LOC = Y2;
NET "ddr0_dq_b[13]" LOC = W1;
NET "ddr0_dq_b[12]" LOC = W3;
NET "ddr0_dq_b[11]" LOC = U1;
NET "ddr0_dq_b[10]" LOC = U3;
NET "ddr0_dq_b[9]" LOC = T1;
NET "ddr0_dq_b[8]" LOC = T2;
NET "ddr0_dq_b[7]" LOC = M1;
NET "ddr0_dq_b[6]" LOC = M2;
NET "ddr0_dq_b[5]" LOC = L1;
NET "ddr0_dq_b[4]" LOC = L3;
NET "ddr0_dq_b[3]" LOC = P1;
NET "ddr0_dq_b[2]" LOC = P2;
NET "ddr0_dq_b[1]" LOC = R1;
NET "ddr0_dq_b[0]" LOC = R3;
NET "ddr0_ba_o[2]" LOC = H1;
NET "ddr0_ba_o[1]" LOC = J1;
NET "ddr0_ba_o[0]" LOC = J3;
NET "ddr0_a_o[13]" LOC = J6;
NET "ddr0_a_o[12]" LOC = F1;
NET "ddr0_a_o[11]" LOC = E1;
NET "ddr0_a_o[10]" LOC = J4;
NET "ddr0_a_o[9]" LOC = G1;
NET "ddr0_a_o[8]" LOC = G3;
NET "ddr0_a_o[7]" LOC = K6;
NET "ddr0_a_o[6]" LOC = L4;
NET "ddr0_a_o[5]" LOC = M3;
NET "ddr0_a_o[4]" LOC = H3;
NET "ddr0_a_o[3]" LOC = M6;
NET "ddr0_a_o[2]" LOC = K5;
NET "ddr0_a_o[1]" LOC = K1;
NET "ddr0_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# FMC slot
#----------------------------------------
......@@ -459,64 +95,52 @@ NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
# PCB LEDs
#----------------------------------------
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# Clocks
#----------------------------------------
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
#----------------------------------------
# Xilinx MCB tweaks
# IOB exceptions
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#----------------------------------------
# Asynchronous resets
# Clocks
#----------------------------------------
# Ignore async reset to DDR controller
NET "ddr0_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "fmc0_adc_dco_p_i" TNM_NET = "fmc0_adc_dco";
NET "fmc0_adc_dco_n_i" TNM_NET = "fmc0_adc_dco";
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr0_ctrl_bank/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
TIMEGRP "fmc_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "fmc_adc_sync_ffs" TIG;
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMEGRP "fmc_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc_adc_sync_reg" 10ns DATAPATHONLY;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 7533c4d0
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
......@@ -14,19 +9,14 @@ syn_top = "wrtd_ref_svec_tdc_fd"
syn_project = "wrtd_ref_svec_tdc_fd.xise"
syn_tool = "ise"
fetchto = "../../../dependencies"
syn_pre_project_cmd = "make -C ../../../software/firmware"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_svec_tdc_fd.ucf",
"buildinfo_pkg.vhd",
]
modules = {
......@@ -34,3 +24,17 @@ modules = {
"../../top/wrtd_ref_svec_tdc_fd",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_template_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
View file @ 7533c4d0
......@@ -2,365 +2,10 @@
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_sysreset_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" LOC = AG26;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" LOC = AH26;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" LOC = AH27;
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
#----------------------------------------
NET "fp_gpio1_o" LOC = T28;
NET "fp_gpio2_o" LOC = R30;
NET "fp_gpio3_i" LOC = V27;
NET "fp_gpio4_i" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_i" IOSTANDARD = "LVCMOS33";
NET "fp_gpio4_i" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMCs
#----------------------------------------
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_acam_refclk_n_i" LOC = "G15";
......@@ -502,7 +147,6 @@ NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_one_wire_b" LOC = "H12";
NET "fmc0_tdc_one_wire_b" IOSTANDARD = "LVCMOS25";
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
......@@ -690,19 +334,8 @@ NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
......@@ -710,59 +343,27 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC template UCF files
# Declaration of domains
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "dcm1_clk_ref_0" TNM_NET = fdl_clk;
NET "tdc_clk_125m" TNM_NET = tdc_clk;
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "clk_sys";
TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "dcm1_clk_ref_0";
TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk_125m";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_rx_rbclk";
TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "fdl_clk";
TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync_ffs" TIG;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "fdl_sync_ffs" TIG;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "tdc_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync_ffs" TIG;
TIMESPEC TS_fdl_sync_ffs = FROM fdl_clk TO "fdl_sync_ffs" TIG;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "clk_125m_pllref";
#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "clk_sys";
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "dcm1_clk_ref_0";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk_125m";
#TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_rx_rbclk";
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_ref_sync_reg = FROM clk_125m_pllref TO "ref_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_sys_sync_reg = FROM clk_sys TO "sys_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_fdl_sync_reg = FROM dcm1_clk_ref_0 TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk_125m TO "tdc_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_reg = FROM phy_rx_rbclk TO "phy_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_fdl_sync_reg = FROM fdl_clk TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
View file @ 7533c4d0
......@@ -4,3 +4,4 @@ Makefile
modelsim.ini
transcript*
*.wlf
buildinfo_pkg.vhd
hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
View file @ 7533c4d0
board = "spec"
sim_tool = "modelsim"
top_module = "main"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
fetchto = "../../../dependencies"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
ctrls = ["bank3_64b_32b"]
include_dirs = [
"../include",
fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/mock-turtle/hdl/testbench/include",
fetchto + "/fmc-adc-100m14b4cha-gw/hdl/testbench/include",
......@@ -23,7 +24,7 @@ include_dirs = [
files = [
"main.sv",
"dut_env.sv",
"synthesis_descriptor.vhd",
"buildinfo_pkg.vhd",
]
modules = {
......@@ -31,3 +32,11 @@ modules = {
"../../top/wrtd_ref_spec150t_adc",
],
}
ctrls = ["bank3_64b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 7533c4d0
......@@ -30,7 +30,6 @@
module dut_env
(
IGN4124PCIMaster i_gn4124,
output[2:0] acq_fsm_state,
output sfp_txp_o, sfp_txn_o,
input sfp_rxp_i, sfp_rxn_i,
input ext_trigger_i
......@@ -87,15 +86,15 @@ module dut_env
.clk_125m_pllref_n_i (~clk_125m_pll),
.clk_125m_gtp_n_i (clk_125m_gtp),
.clk_125m_gtp_p_i (~clk_125m_gtp),
.pll25dac_sync_n_o (),
.pll20dac_sync_n_o (),
.pll25dac_cs_n_o (),
.pll20dac_cs_n_o (),
.plldac_din_o (),
.plldac_sclk_o (),
.led_sfp_red_o (),
.led_sfp_green_o (),
.led_act_o (),
.led_link_o (),
.aux_leds_o (),
.pcbrev_i (4'b0),
.carrier_onewire_b (),
.onewire_b (),
.sfp_txp_o (sfp_txp_o),
.sfp_txn_o (sfp_txn_o),
.sfp_rxp_i (sfp_rxp_i),
......@@ -135,24 +134,24 @@ module dut_env
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b (),
.ddr0_a_o (ddr_a),
.ddr0_ba_o (ddr_ba),
.ddr0_cas_n_o (ddr_cas_n),
.ddr0_ck_n_o (ddr_ck_n),
.ddr0_ck_p_o (ddr_ck_p),
.ddr0_cke_o (ddr_cke),
.ddr0_dq_b (ddr_dq),
.ddr0_ldm_o (ddr_dm[0]),
.ddr0_ldqs_n_b (ddr_dqs_n[0]),
.ddr0_ldqs_p_b (ddr_dqs_p[0]),
.ddr0_odt_o (ddr_odt),
.ddr0_ras_n_o (ddr_ras_n),
.ddr0_reset_n_o (ddr_reset_n),
.ddr0_rzq_b (ddr_rzq),
.ddr0_udm_o (ddr_dm[1]),
.ddr0_udqs_n_b (ddr_dqs_n[1]),
.ddr0_udqs_p_b (ddr_dqs_p[1]),
.ddr0_we_n_o (ddr_we_n),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n),
.fmc0_adc_ext_trigger_p_i (ext_trigger_i),
.fmc0_adc_ext_trigger_n_i (~ext_trigger_i),
.fmc0_adc_dco_p_i (clk_400m_adc),
......@@ -187,8 +186,6 @@ module dut_env
.fmc0_sda_b ()
);
assign acq_fsm_state = DUT.cmp0_fmc_adc_mezzanine.cmp_fmc_adc_100Ms_core.acq_fsm_state;
//---------------------------------------------------------------------------
// DDR memory model
//---------------------------------------------------------------------------
......@@ -291,16 +288,16 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.inst_spec_template.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
......
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ 7533c4d0
......@@ -28,9 +28,11 @@
`include "wrtd_driver.svh"
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_alt_trigout.v"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
`define ADC_CSR_BASE 'h5000
`define ADC_EIC_BASE 'h5500
module main;
......@@ -38,10 +40,9 @@ module main;
IGN4124PCIMaster hostB ();
reg duta_ext_trig, dutb_ext_trig;
wire[2:0] duta_acq_state, dutb_acq_state;
dut_env DUTA (hostA, duta_acq_state, a2b_txp, a2b_txn, a2b_rxp, a2b_rxn, duta_ext_trig);
dut_env DUTB (hostB, dutb_acq_state, a2b_rxp, a2b_rxn, a2b_txp, a2b_txn, dutb_ext_trig);
dut_env DUTA (hostA, a2b_txp, a2b_txn, a2b_rxp, a2b_rxn, duta_ext_trig);
dut_env DUTB (hostB, a2b_rxp, a2b_rxn, a2b_txp, a2b_txn, dutb_ext_trig);
IMockTurtleIRQ MtIrqMonitorA (`MT_ATTACH_IRQ(DUTA.DUT.cmp_mock_turtle));
IMockTurtleIRQ MtIrqMonitorB (`MT_ATTACH_IRQ(DUTB.DUT.cmp_mock_turtle));
......@@ -52,6 +53,8 @@ module main;
const uint64_t MT_BASE = 'h0002_0000;
int sim_end = 0;
initial begin
uint64_t val, expected;
......@@ -72,21 +75,27 @@ module main;
devA.set_rule ( "rule0", "LC-I5", "NET0", 0 );
devA.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accA.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accA.write(`VIC_BASE + 'h8, 'h7f);
accA.write(`VIC_BASE + 'h0, 'h1);
// Config DUTA to trigger on external trigger and get 64 samples
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h8000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39;
......@@ -95,7 +104,6 @@ module main;
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:A] <%t> ADC configured and armed", $realtime);
wait (duta_acq_state == 1);
end
begin
......@@ -107,29 +115,32 @@ module main;
devB.set_rule ( "rule0", "NET0", "LC-O1", 50000 );
devB.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accB.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accB.write(`VIC_BASE + 'h8, 'h7f);
accB.write(`VIC_BASE + 'h0, 'h1);
// Config DUTB to trigger on WRTD and get 64 samples
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h01);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h8000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h7fff);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39;
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:B] <%t> ADC configured and armed", $realtime);
wait (dutb_acq_state == 1);
end
join
......@@ -147,59 +158,68 @@ module main;
fork
begin
wait (duta_acq_state == 1);
wait (DUTA.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:A] <%t> END ACQ 1", $realtime);
accA.write(`ADC_EIC_BASE + 'hc, 'h2);
accA.write(`VIC_BASE + 'h1c, 'h0);
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:A] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accA.write('h2008, val); // dma start addr
accA.write(`DMA_BASE + 'h08, val); // dma start addr
accA.write('h200C, 'h00001000); // host addr
accA.write('h2010, 'h00000000);
accA.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accA.write(`DMA_BASE + 'h10, 'h00000000);
accA.write('h2014, 'h00000100); // len << 2
accA.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accA.write('h2018, 'h00000000); // next
accA.write('h201C, 'h00000000);
accA.write(`DMA_BASE + 'h18, 'h00000000); // next
accA.write(`DMA_BASE + 'h1C, 'h00000000);
accA.write('h2020, 'h00000000); // attrib: pcie -> host
accA.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accA.write('h2000, 'h00000001); // xfer start
accA.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTA.DUT.dma_irq[0] == 1);
wait (DUTA.DUT.inst_spec_template.irqs[2] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime);
accA.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accA.write(`VIC_BASE + 'h1c, 'h0);
end
begin
wait (dutb_acq_state == 1);
wait (DUTB.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:B] <%t> END ACQ 1", $realtime);
accB.write(`ADC_EIC_BASE + 'hc, 'h2);
accB.write(`VIC_BASE + 'h1c, 'h0);
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:B] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accB.write('h2008, val); // dma start addr
accB.write(`DMA_BASE + 'h08, val); // dma start addr
accB.write('h200C, 'h00001000); // host addr
accB.write('h2010, 'h00000000);
accB.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accB.write(`DMA_BASE + 'h10, 'h00000000);
accB.write('h2014, 'h00000100); // len << 2
accB.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accB.write('h2018, 'h00000000); // next
accB.write('h201C, 'h00000000);
accB.write(`DMA_BASE + 'h18, 'h00000000); // next
accB.write(`DMA_BASE + 'h1C, 'h00000000);
accB.write('h2020, 'h00000000); // attrib: pcie -> host
accB.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accB.write('h2000, 'h00000001); // xfer start
accB.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTB.DUT.dma_irq[0] == 1);
wait (DUTB.DUT.inst_spec_template.irqs[2] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime);
accB.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accB.write(`VIC_BASE + 'h1c, 'h0);
end
join
sim_end = 1;
end
......@@ -219,7 +239,7 @@ module main;
$display("-------------------");
$display();
#5000us;
wait (sim_end == 1);
$display();
$display("Simulation PASSED");
......
hdl/testbench/wrtd_ref_spec150t_adc/synthesis_descriptor.vhd deleted 100644 → 0
View file @ 0c081bed
--------------------------------------------------------------------------------
-- SDB meta information for wrtd_ref_spec150t_adc.xise.
--
-- This file was automatically generated by ../../../dependencies/general-cores/tools/sdb_desc_gen.tcl on:
-- Wednesday, January 30 2019
--
-- ../../../dependencies/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := (
syn_module_name => "wrtd_ref_spec150",
syn_commit_id => "eaa378a35717954407166b2e80e34c2*",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20190130",
syn_username => "Dimitris Lampri");
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "git@ohwr-gitlab.cern.ch:project/wrtd.git ");
end package synthesis_descriptor;
hdl/testbench/wrtd_ref_svec_tdc_fd/.gitignore
View file @ 7533c4d0
......@@ -3,3 +3,4 @@ Makefile
modelsim.ini
transcript*
*.wlf
buildinfo_pkg.vhd
hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 7533c4d0
......@@ -6,7 +6,10 @@ target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
fetchto="../../../dependencies"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
......@@ -14,12 +17,13 @@ include_dirs = [
"../include",
fetchto + "/general-cores/sim/",
fetchto + "/mock-turtle/hdl/testbench/include/",
fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
]
files = [
"main.sv",
"dut_env.sv",
"synthesis_descriptor.vhd",
"buildinfo_pkg.vhd",
]
modules = {
......@@ -27,3 +31,13 @@ modules = {
"../../top/wrtd_ref_svec_tdc_fd",
],
}
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
svec_template_ucf = []
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @ 7533c4d0
......@@ -25,7 +25,8 @@
`timescale 1ns/1ps
`include "vhd_wishbone_master.svh"
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
module simple_tdc_driver
(
......@@ -211,7 +212,7 @@ endmodule // simple_fdelay_mon
module dut_env
(
IVHDWishboneMaster host,
IVME64X VME,
output clk_sys, rst_sys_n,
sfp_txp_o, sfp_txn_o,
input sfp_rxp_i, sfp_rxn_i
......@@ -247,24 +248,47 @@ module dut_env
// The DUT
//---------------------------------------------------------------------------
`DECLARE_VME_BUFFERS(VME.slave);
bit [4:0] slot_id = 8;
wrtd_ref_svec_tdc_fd #
(
.g_SIMULATION (1),
.g_SIM_BYPASS_VME (1),
.g_WRPC_INITF ("../../../dependencies/wr-cores/bin/wrpc/wrc_phy8_sim.bram")
)
DUT
(
.rst_n_i (1'b1),
.vme_sysreset_n_i (1'b1),
.vme_sysreset_n_i (VME_RST_n),
.vme_as_n_i (VME_AS_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
.vme_gap_i (^slot_id),
.vme_ga_i (~slot_id),
.vme_berr_o (VME_BERR),
.vme_dtack_n_o (VME_DTACK_n),
.vme_retry_n_o (VME_RETRY_n),
.vme_retry_oe_o (VME_RETRY_OE),
.vme_lword_n_b (VME_LWORD_n),
.vme_addr_b (VME_ADDR),
.vme_data_b (VME_DATA),
.vme_irq_o (VME_IRQ_n),
.vme_iack_n_i (VME_IACK_n),
.vme_iackin_n_i (VME_IACKIN_n),
.vme_iackout_n_o (VME_IACKOUT_n),
.vme_dtack_oe_o (VME_DTACK_OE),
.vme_data_dir_o (VME_DATA_DIR),
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N),
.clk_125m_pllref_p_i (clk_125m_pll),
.clk_125m_pllref_n_i (~clk_125m_pll),
.clk_125m_gtp_p_i (clk_125m_gtp),
.clk_125m_gtp_n_i (~clk_125m_gtp),
.clk_20m_vcxo_i (clk_20m_vcxo),
.sim_wb_i (host.out),
.sim_wb_o (host.in),
.carrier_onewire_b (),
.onewire_b (),
.sfp_txp_o (sfp_txp_o),
.sfp_txn_o (sfp_txn_o),
.sfp_rxp_i (sfp_rxp_i),
......@@ -363,7 +387,7 @@ module dut_env
initial begin
// No pulse before: WR (300us) + TDC setup.
automatic time start = 480us;
automatic time start = 850us;
push_pulse(0, start + 10us);
push_pulse(1, start + 30us);
......@@ -376,16 +400,16 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
......
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @ 7533c4d0
......@@ -24,10 +24,13 @@
`timescale 1ns/1ps
`include "vme64x_bfm.svh"
`include "wrtd_driver.svh"
`include "vhd_wishbone_master.svh"
`define TDC_DIRECT_BASE 'h18000
`define VME_OFFSET 'h8000_0000
`define TDC_DIRECT_BASE `VME_OFFSET + 'h0001_8000
`define MT_BASE `VME_OFFSET + 'h0002_0000
module main;
......@@ -35,9 +38,9 @@ module main;
wire sfp_txp, sfp_txn, sfp_rxp, sfp_rxn;
IVHDWishboneMaster host (clk_sys, rst_sys_n);
IVME64X VME(rst_sys_n);
dut_env DUT (host, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
dut_env DUT (VME, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
IMockTurtleIRQ MtIrqMonitor (`MT_ATTACH_IRQ(DUT.DUT.cmp_mock_turtle));
......@@ -46,18 +49,35 @@ module main;
WrtdDrv dev;
const uint64_t MT_BASE = 'h0002_0000;
initial begin
CBusAccessor acc;
CBusAccessor_VME64x acc;
initial begin
acc = new(VME.tb);
$timeformat (-6, 3, "us", 10);
#10us;
acc = host.get_accessor();
acc.set_default_xfer_size(4);
dev = new (acc, MT_BASE, MtIrqMonitor, "DUT");
#5us;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
/* Hack around CBusAccessor to make it work like CBusAccessor_VME64x. This is needed
because WrtdDev expects a CBusAccesor and will not respect the m_default_modifiers value
of CBusAccessor_VME64x when performing reads/writes. */
acc.set_default_xfer_size(A32 | D32 | SINGLE);
acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
#5us;
dev = new (acc, `MT_BASE, MtIrqMonitor, "DUT");
dev.init();
dev.add_rule ( "rule0" );
......@@ -86,8 +106,19 @@ module main;
// Set dead-time
acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
#5us;
// Enable channels
acc.write(`TDC_DIRECT_BASE + 'h0, 'h1f);
// Force start_fpga from TDC to make sure that the FSM has been started
force DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga = 'b1;
#100ns;
release DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga;
dev.mdisplay("Configuration complete, ready to accept pulses...");
end
initial begin
......
hdl/testbench/wrtd_ref_svec_tdc_fd/synthesis_descriptor.vhd deleted 100644 → 0
View file @ 0c081bed
--------------------------------------------------------------------------------
-- SDB meta information for svec_list_tdc_fd.xise.
--
-- This file was automatically generated by ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Friday, July 20 2018
--
-- ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := (
syn_module_name => "svec_list_tdc_fd",
syn_commit_id => "4a68a12eede44d878435d25c3c7eaaf4",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20180720",
syn_username => "Dimitris Lampri");
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "ssh://git@gitlab.cern.ch:7999/coht/wr-trigger-distribution.git ");
end package synthesis_descriptor;
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
View file @ 7533c4d0
files = [
"wrtd_ref_spec150t_adc.vhd",
"carrier_csr_wbgen2_pkg.vhd",
"carrier_csr.vhd",
"dma_eic.vhd",
]
fetchto = "../../../dependencies"
......@@ -15,6 +12,7 @@ modules = {
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git",
],
}
hdl/top/wrtd_ref_spec150t_adc/carrier_csr.vhd deleted 100644 → 0
View file @ 0c081bed
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Jan 30 13:16:24 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.carrier_csr_wbgen2_pkg.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_carrier_csr_in_registers;
regs_o : out t_carrier_csr_out_registers
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= regs_i.carrier_reserved_i;
rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.stat_fmc_pres_i;
rddata_reg(1) <= regs_i.stat_p2l_pll_lck_i;
rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
rddata_reg(3) <= regs_i.stat_ddr3_cal_done_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Green LED
regs_o.ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- State of the reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/wrtd_ref_spec150t_adc/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 0c081bed
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Jan 30 13:16:24 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package carrier_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_carrier_csr_in_registers is record
carrier_pcb_rev_i : std_logic_vector(3 downto 0);
carrier_reserved_i : std_logic_vector(11 downto 0);
carrier_type_i : std_logic_vector(15 downto 0);
stat_fmc_pres_i : std_logic;
stat_p2l_pll_lck_i : std_logic;
stat_sys_pll_lck_i : std_logic;
stat_ddr3_cal_done_i : std_logic;
end record;
constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
carrier_pcb_rev_i => (others => '0'),
carrier_reserved_i => (others => '0'),
carrier_type_i => (others => '0'),
stat_fmc_pres_i => '0',
stat_p2l_pll_lck_i => '0',
stat_sys_pll_lck_i => '0',
stat_ddr3_cal_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_carrier_csr_out_registers is record
ctrl_led_green_o : std_logic;
ctrl_led_red_o : std_logic;
ctrl_dac_clr_n_o : std_logic;
rst_fmc0_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_led_green_o => '0',
ctrl_led_red_o => '0',
ctrl_dac_clr_n_o => '0',
rst_fmc0_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body carrier_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
variable tmp: t_carrier_csr_in_registers;
begin
tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
tmp.stat_fmc_pres_i := f_x_to_zero(left.stat_fmc_pres_i) or f_x_to_zero(right.stat_fmc_pres_i);
tmp.stat_p2l_pll_lck_i := f_x_to_zero(left.stat_p2l_pll_lck_i) or f_x_to_zero(right.stat_p2l_pll_lck_i);
tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
tmp.stat_ddr3_cal_done_i := f_x_to_zero(left.stat_ddr3_cal_done_i) or f_x_to_zero(right.stat_ddr3_cal_done_i);
return tmp;
end function;
end package body;
hdl/top/wrtd_ref_spec150t_adc/dma_eic.vhd deleted 100644 → 0
View file @ 0c081bed
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for GN4124 DMA enhanced interrupt controller
---------------------------------------------------------------------------------------
-- File : ../dma_eic.vhd
-- Author : auto-generated by wbgen2 from dma_eic.wb
-- Created : Wed Jan 30 13:16:24 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity dma_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic
);
end dma_eic;
architecture syn of dma_eic is
signal eic_idr_int : std_logic_vector(1 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(1 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(1 downto 0);
signal eic_isr_clear_int : std_logic_vector(1 downto 0);
signal eic_isr_status_int : std_logic_vector(1 downto 0);
signal eic_irq_ack_int : std_logic_vector(1 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(1 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= eic_imr_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(1 downto 0) <= eic_isr_status_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 2,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_dma_done_i;
irq_inputs_vector_int(1) <= irq_dma_error_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/wrtd_ref_spec150t_adc/wb_gen/Makefile deleted 100644 → 0
View file @ 0c081bed
WBGEN2 = $(shell which wbgen2)
RTL = ..
all: carrier_csr dma_eic
carrier_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)/$@.vhd -p $(RTL)/$@_wbgen2_pkg.vhd $@.wb
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)/$@.vhd $@.wb
hdl/top/wrtd_ref_spec150t_adc/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 0c081bed
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Manual control of the front panel green LED (unused in the fmc-adc application)";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Manual control of the front panel red LED (unused in the fmc-adc application)";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanine including the ddr interface and the time-tagging core.";
field {
name = "State of the reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
};
};
hdl/top/wrtd_ref_spec150t_adc/wb_gen/dma_eic.wb deleted 100644 → 0
View file @ 0c081bed
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 7533c4d0
......@@ -33,18 +33,10 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.gn4124_core_pkg.all;
use work.carrier_csr_wbgen2_pkg.all;
use work.mt_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.synthesis_descriptor.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.wr_fabric_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.ddr3_ctrl_pkg.all;
entity wrtd_ref_spec150t_adc is
generic (
......@@ -69,14 +61,14 @@ entity wrtd_ref_spec150t_adc is
clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs
led_sfp_red_o : out std_logic;
led_sfp_green_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
......@@ -85,7 +77,7 @@ entity wrtd_ref_spec150t_adc is
pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
......@@ -113,8 +105,8 @@ entity wrtd_ref_spec150t_adc is
------------------------------------------
-- GN4124 interface
--
-- gn_gpio_b[0] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[1] -> U16 -> GN4124 GPIO8
-- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
......@@ -142,24 +134,24 @@ entity wrtd_ref_spec150t_adc is
------------------------------------------
-- DDR (bank 3)
------------------------------------------
ddr0_a_o : out std_logic_vector(13 downto 0);
ddr0_ba_o : out std_logic_vector(2 downto 0);
ddr0_cas_n_o : out std_logic;
ddr0_ck_n_o : out std_logic;
ddr0_ck_p_o : out std_logic;
ddr0_cke_o : out std_logic;
ddr0_dq_b : inout std_logic_vector(15 downto 0);
ddr0_ldm_o : out std_logic;
ddr0_ldqs_n_b : inout std_logic;
ddr0_ldqs_p_b : inout std_logic;
ddr0_odt_o : out std_logic;
ddr0_ras_n_o : out std_logic;
ddr0_reset_n_o : out std_logic;
ddr0_rzq_b : inout std_logic;
ddr0_udm_o : out std_logic;
ddr0_udqs_n_b : inout std_logic;
ddr0_udqs_p_b : inout std_logic;
ddr0_we_n_o : out std_logic;
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
------------------------------------------
-- FMC slots
......@@ -199,8 +191,6 @@ entity wrtd_ref_spec150t_adc is
fmc0_adc_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
-- FMC slot management
fmc0_prsnt_m2c_n_i : in std_logic;
......@@ -216,122 +206,35 @@ architecture arch of wrtd_ref_spec150t_adc is
-- Constants
-----------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 3 + 4;
constant c_NUM_WB_SLAVES : integer := 3;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_GENNUM : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_SPEC_CSR : integer := 0;
constant c_WB_SLAVE_VIC : integer := 1;
constant c_WB_SLAVE_BASE : integer := 2;
constant c_WB_SLAVE_DMA : integer := c_WB_SLAVE_BASE + 0;
constant c_WB_SLAVE_DMA_EIC : integer := c_WB_SLAVE_BASE + 1;
constant c_WB_SLAVE_FMC_ADC : integer := c_WB_SLAVE_BASE + 2;
constant c_WB_SLAVE_MT : integer := c_WB_SLAVE_BASE + 0 + 3;
constant c_WB_SLAVE_WRC : integer := c_WB_SLAVE_BASE + 1 + 3;
constant c_WB_DESC_SYN : integer := c_WB_SLAVE_BASE + 2 + 3;
constant c_WB_DESC_URL : integer := c_WB_SLAVE_BASE + 3 + 3;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_WB_SPEC_CSR_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_FMC_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_WB_DMA_CTRL_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_WB_DMA_EIC_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_SDB_ENDIAN_BIG,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d5735ab4", -- echo "WB-DMA.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-DMA.EIC ")));
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_ADC : integer := 1;
constant c_WB_SLAVE_MT : integer := 2;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_WB_SPEC_CSR_SDB, x"00001000"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001200"),
c_WB_SLAVE_DMA => f_sdb_embed_device(c_WB_DMA_CTRL_SDB, x"00002000"),
c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_WB_DMA_EIC_SDB, x"00002200"),
c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_FMC_BRIDGE_SDB, x"00004000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
-- not really used, will be reprogrammed by software
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
0 => x"00005500", -- FMC EIC
1 => x"00002200", -- DMA EIC
2 => x"00020000", -- MT Mqueue in interrupt
3 => x"00020001", -- MT Mqueue out interrupt
4 => x"00020002", -- MT Console interrupt
5 => x"00020003"); -- MT Notify interrupt
constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
(0 => x"00000000");
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000");
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_ADC => x"0000_4000",
c_WB_SLAVE_MT => x"0002_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FMC_ADC => x"0003_e000", -- 0x2000 bytes
c_WB_SLAVE_MT => x"0002_0000"); -- 0x20000 bytes
constant c_MT_CONFIG : t_mt_config :=
(
......@@ -372,29 +275,9 @@ architecture arch of wrtd_ref_spec150t_adc is
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
signal sw_rst_fmc : std_logic := '1';
signal sw_rst_fmc_sync : std_logic := '1';
signal fmc_rst_ref_125m_n : std_logic := '0';
signal fmc_rst_sys_n : std_logic := '0';
signal ddr0_rst : std_logic := '1';
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr0_rst : signal is "TRUE";
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
signal gn4124_access : std_logic;
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -408,38 +291,6 @@ architecture arch of wrtd_ref_spec150t_adc is
signal gn_wb_ddr_in : t_wishbone_master_in;
signal gn_wb_ddr_out : t_wishbone_master_out;
-- Interrupts and status
signal dma_irq : std_logic_vector(1 downto 0);
signal fmc_host_irq : std_logic_vector(0 downto 0) := "0";
signal mt_hmq_in_irq : std_logic;
signal mt_hmq_out_irq : std_logic;
signal mt_console_irq : std_logic;
signal mt_notify_irq : std_logic;
signal vic_master_irq : std_logic;
-- Front panel LED control
signal led_red : std_logic;
signal led_green : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
-- MT endpoints
signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
signal rmq_endpoint_in : t_mt_rmq_endpoint_iface_in;
......@@ -462,28 +313,18 @@ architecture arch of wrtd_ref_spec150t_adc is
signal fmc_dp_wb_out : t_wishbone_master_out;
signal fmc_dp_wb_in : t_wishbone_master_in;
-- WRPC TM interface and aux clocks
-- WRPC TM interface and status
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
signal tm_clk_aux_locked : std_logic_vector(1 downto 0) := "00";
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic_vector(1 downto 0);
signal tm_time_valid_sync : std_logic;
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
-- MT TM interface
signal tm : t_mt_timing_if;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_in_registers;
signal csr_regout : t_carrier_csr_out_registers;
constant g_FMC0_MULTISHOT_RAM_SIZE : natural := 2048;
constant g_FMC0_CALIB_SOFT_IP : string := "TRUE";
-- Wishbone bus from cross-clocking module to FMC0 mezzanine
signal cnx_fmc0_sync_master_out : t_wishbone_master_out;
signal cnx_fmc0_sync_master_in : t_wishbone_master_in;
......@@ -499,177 +340,161 @@ architecture arch of wrtd_ref_spec150t_adc is
signal fmc0_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal ddr0_wr_fifo_empty : std_logic;
signal ddr0_wr_fifo_empty_sync : std_logic;
signal fmc0_irq : std_logic;
signal tm_time_valid_sync : std_logic;
-- Conversion of g_simulation to string needed for DDR controller
function fmc0_f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_FMC0_SIMULATION_STR : string :=
fmc0_f_int2string(g_SIMULATION);
-- DDR
signal ddr0_status : std_logic_vector(31 downto 0);
signal ddr0_calib_done : std_logic;
signal ddr0_addr_cnt : unsigned(31 downto 0);
signal ddr0_dat_cyc_d : std_logic;
signal ddr0_addr_cnt_en : std_logic;
-- Interrupts and status
signal dma_eic_irq : std_logic;
-- Resync interrupts to sys domain
signal dma_irq_sync : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty_sync : std_logic;
signal fmc_irq_sync : std_logic;
signal ddr_wr_fifo_empty : std_logic;
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(4 downto 0);
signal gn4124_access : std_logic;
begin -- architecture arch
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
sys_clk_pll_locked <= '1';
-- reset for mezzanine
-- including soft reset, with re-sync from 62.5MHz domain
-- and registers to help with timing
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => sw_rst_fmc,
synced_o => sw_rst_fmc_sync);
fmc_rst_ref_125m_n <= rst_ref_125m_n and not sw_rst_fmc_sync;
fmc_rst_sys_n <= rst_sys_62m5_n and not sw_rst_fmc;
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr0_rst <= not rst_ddr_333m_n or sw_rst_fmc;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_0001", -- WRTD Node (WN) 1
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).ack,
wb_stall_o => open,
regs_i => csr_regin,
regs_o => csr_regout);
csr_regin.carrier_pcb_rev_i <= pcbrev_i;
csr_regin.carrier_reserved_i <= (others => '0');
csr_regin.carrier_type_i <= c_CARRIER_TYPE;
csr_regin.stat_fmc_pres_i <= fmc0_prsnt_m2c_n_i;
csr_regin.stat_p2l_pll_lck_i <= gn4124_status(0);
csr_regin.stat_sys_pll_lck_i <= sys_clk_pll_locked;
csr_regin.stat_ddr3_cal_done_i <= ddr0_calib_done;
led_red <= csr_regout.ctrl_led_red_o;
led_green <= csr_regout.ctrl_led_green_o;
sw_rst_fmc <= csr_regout.rst_fmc0_o;
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).err <= '0';
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).rty <= '0';
cnx_slave_out(c_WB_SLAVE_SPEC_CSR).stall <= '0';
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : xwb_gn4124_core
inst_spec_base : entity work.spec_base_wr
generic map (
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 64,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 0,
g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION))
port map (
rst_n_a_i => gn_rst_n_i,
status_o => gn4124_status,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
l2p_clk_p_o => gn_l2p_clk_p_o,
l2p_clk_n_o => gn_l2p_clk_n_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
vc_rdy_i => gn_vc_rdy_i,
dma_irq_o => dma_irq,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
wb_master_clk_i => clk_sys_62m5,
wb_master_rst_n_i => rst_sys_62m5_n,
wb_master_i => cnx_master_in(c_WB_MASTER_GENNUM),
wb_master_o => cnx_master_out(c_WB_MASTER_GENNUM),
wb_dma_cfg_clk_i => clk_sys_62m5,
wb_dma_cfg_rst_n_i => rst_sys_62m5_n,
wb_dma_cfg_i => cnx_slave_in(c_WB_SLAVE_DMA),
wb_dma_cfg_o => cnx_slave_out(c_WB_SLAVE_DMA),
wb_dma_dat_clk_i => clk_sys_62m5,
wb_dma_dat_rst_n_i => rst_sys_62m5_n,
wb_dma_dat_i => gn_wb_ddr_in,
wb_dma_dat_o => gn_wb_ddr_out);
-- Assign unused outputs
gn_gpio_b(0) <= '0';
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_cyc_i => fmc0_wb_ddr_out.cyc,
ddr_dma_wb_stb_i => fmc0_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc0_wb_ddr_out.adr,
ddr_dma_wb_sel_i => fmc0_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc0_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc0_wb_ddr_out.dat,
ddr_dma_wb_ack_o => fmc0_wb_ddr_in.ack,
ddr_dma_wb_stall_o => fmc0_wb_ddr_in.stall,
ddr_dma_wb_dat_o => fmc0_wb_ddr_in.dat,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
fmc0_wb_ddr_in.err <= '0';
fmc0_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
cmp_crossbar : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_WB_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......@@ -678,29 +503,6 @@ begin -- architecture arch
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-----------------------------------------------------------------------------
-- Vectored Interrupt Controller (WB Slave)
-----------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map (
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_NUM_INTERRUPTS => 6,
g_INIT_VECTORS => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_host_irq(0),
irqs_i(1) => dma_eic_irq,
irqs_i(2) => mt_hmq_in_irq,
irqs_i(3) => mt_hmq_out_irq,
irqs_i(4) => mt_console_irq,
irqs_i(5) => mt_notify_irq,
irq_master_o => vic_master_irq);
-----------------------------------------------------------------------------
-- Mock Turtle (WB Slave)
-----------------------------------------------------------------------------
......@@ -723,17 +525,16 @@ begin -- architecture arch
host_slave_o => cnx_slave_out(c_WB_SLAVE_MT),
clk_ref_i => clk_ref_125m,
tm_i => tm,
hmq_in_irq_o => mt_hmq_in_irq,
hmq_out_irq_o => mt_hmq_out_irq,
notify_irq_o => mt_notify_irq,
console_irq_o => mt_console_irq);
tm.cycles <= tm_cycles;
tm.tai <= tm_tai;
tm.time_valid <= tm_time_valid;
tm.link_up <= tm_link_up;
tm.aux_locked(1 downto 0) <= tm_clk_aux_locked;
tm.aux_locked(7 downto 2) <= (others => '0');
hmq_in_irq_o => irq_vector(1),
hmq_out_irq_o => irq_vector(2),
notify_irq_o => irq_vector(4),
console_irq_o => irq_vector(3));
tm.cycles <= tm_cycles;
tm.tai <= tm_tai;
tm.time_valid <= tm_time_valid;
tm.link_up <= tm_link_up;
tm.aux_locked <= (others => '0');
cmp_eth_endpoint : entity work.mt_ep_ethernet_single
port map (
......@@ -772,131 +573,6 @@ begin -- architecture arch
end process p_rmq_assign;
-----------------------------------------------------------------------------
-- The WR PTP core SVEC board package (WB Slave)
-----------------------------------------------------------------------------
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_SIMULATION => g_SIMULATION,
g_VERBOSE => FALSE,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
areset_n_i => button1_n_i,
areset_edge_n_i => gn_rst_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o,
pll20dac_cs_n_o => pll20dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
flash_sclk_o => spi_sclk_o,
flash_ncs_o => spi_ncs_o,
flash_mosi_o => spi_mosi_o,
flash_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => open,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier OneWire
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
gen_dma_irq : for I in 0 to 1 generate
cmp_dma_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => dma_irq(I),
synced_o => dma_irq_sync(I));
end generate gen_dma_irq;
cmp_dma_eic : entity work.dma_eic
port map (
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq_sync(0),
irq_dma_error_i => dma_irq_sync(1)
);
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_slave_out(c_WB_SLAVE_DMA_EIC).rty <= '0';
cmp_fmc0_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc0_irq,
synced_o => fmc_host_irq(0));
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
-- Mezzanine system managment I2C master
......@@ -917,13 +593,6 @@ begin -- architecture arch
master_i => cnx_fmc0_sync_master_in,
master_o => cnx_fmc0_sync_master_out);
cmp0_fmc_ddr_wr_fifo_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => ddr0_wr_fifo_empty,
synced_o => ddr0_wr_fifo_empty_sync);
cmp0_tm_time_valid_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
......@@ -931,9 +600,16 @@ begin -- architecture arch
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp0_fmc_irq_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc0_irq,
synced_o => irq_vector(0));
cmp0_fmc_adc_mezzanine : entity work.fmc_adc_mezzanine
generic map (
g_MULTISHOT_RAM_SIZE => g_FMC0_MULTISHOT_RAM_SIZE,
g_MULTISHOT_RAM_SIZE => 2048,
g_SPARTAN6_USE_PLL => FALSE,
g_TRIG_DELAY_EXT => 7,
g_TRIG_DELAY_SW => 10,
......@@ -952,7 +628,7 @@ begin -- architecture arch
wb_ddr_master_i => fmc0_wb_ddr_in,
wb_ddr_master_o => fmc0_wb_ddr_out,
ddr_wr_fifo_empty_i => ddr0_wr_fifo_empty_sync,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => open,
acq_end_irq_o => open,
eic_irq_o => fmc0_irq,
......@@ -1007,112 +683,6 @@ begin -- architecture arch
wr_tm_cycles_i => tm_cycles,
wr_enable_i => wrabbit_en);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr0_ctrl_bank : ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_FMC0_SIMULATION_STR,
g_CALIB_SOFT_IP => g_FMC0_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => ddr0_rst,
status_o => ddr0_status,
ddr3_dq_b => ddr0_dq_b,
ddr3_a_o => ddr0_a_o,
ddr3_ba_o => ddr0_ba_o,
ddr3_ras_n_o => ddr0_ras_n_o,
ddr3_cas_n_o => ddr0_cas_n_o,
ddr3_we_n_o => ddr0_we_n_o,
ddr3_odt_o => ddr0_odt_o,
ddr3_rst_n_o => ddr0_reset_n_o,
ddr3_cke_o => ddr0_cke_o,
ddr3_dm_o => ddr0_ldm_o,
ddr3_udm_o => ddr0_udm_o,
ddr3_dqs_p_b => ddr0_ldqs_p_b,
ddr3_dqs_n_b => ddr0_ldqs_n_b,
ddr3_udqs_p_b => ddr0_udqs_p_b,
ddr3_udqs_n_b => ddr0_udqs_n_b,
ddr3_clk_p_o => ddr0_ck_p_o,
ddr3_clk_n_o => ddr0_ck_n_o,
ddr3_rzq_b => ddr0_rzq_b,
wb0_rst_n_i => fmc_rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => fmc0_wb_ddr_out.sel,
wb0_cyc_i => fmc0_wb_ddr_out.cyc,
wb0_stb_i => fmc0_wb_ddr_out.stb,
wb0_we_i => fmc0_wb_ddr_out.we,
wb0_addr_i => fmc0_wb_ddr_out.adr,
wb0_data_i => fmc0_wb_ddr_out.dat,
wb0_data_o => fmc0_wb_ddr_in.dat,
wb0_ack_o => fmc0_wb_ddr_in.ack,
wb0_stall_o => fmc0_wb_ddr_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr0_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
wb1_we_i => gn_wb_ddr_out.we,
wb1_addr_i => gn_wb_ddr_out.adr,
wb1_data_i => gn_wb_ddr_out.dat,
wb1_data_o => gn_wb_ddr_in.dat,
wb1_ack_o => gn_wb_ddr_in.ack,
wb1_stall_o => gn_wb_ddr_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open);
fmc0_wb_ddr_in.err <= '0';
fmc0_wb_ddr_in.rty <= '0';
cmp_ddr0_calib_done_sync : gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => ddr0_status(0),
synced_o => ddr0_calib_done);
-- unused Wishbone signals
gn_wb_ddr_in.err <= '0';
gn_wb_ddr_in.rty <= '0';
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu0_crossbar : xwb_crossbar
generic map (
......@@ -1153,8 +723,4 @@ begin -- architecture arch
aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led;
-- SPEC front panel leds
led_sfp_red_o <= led_red or wr_led_act;
led_sfp_green_o <= led_green or wr_led_link;
end architecture arch;
hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 7533c4d0
......@@ -6,6 +6,7 @@ fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
......@@ -13,5 +14,6 @@ modules = {
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @ 7533c4d0
......@@ -37,15 +37,10 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.wr_fabric_pkg.all;
use work.mt_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.tdc_core_pkg.all;
use work.fine_delay_pkg.all;
use work.synthesis_descriptor.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
library unisim;
use unisim.vcomponents.all;
......@@ -59,9 +54,7 @@ entity wrtd_ref_svec_tdc_fd is
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
-- to speed up simulations.
g_SIMULATION : integer := 0;
-- Bypass VME core, useful only in simulation
g_SIM_BYPASS_VME : boolean := FALSE);
g_SIMULATION : integer := 0);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -83,12 +76,6 @@ entity wrtd_ref_svec_tdc_fd is
-- VME interface
---------------------------------------------------------------------------
-- Bypass VME core, useful only in simulation
-- synthesis translate_off
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out;
-- synthesis translate_on
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
......@@ -147,11 +134,16 @@ entity wrtd_ref_svec_tdc_fd is
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- PCB version
---------------------------------------------------------------------------
pcbrev_i : in std_logic_vector(4 downto 0);
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
......@@ -178,10 +170,10 @@ entity wrtd_ref_svec_tdc_fd is
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
fp_gpio1_o : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- Ref clock div2 output
fp_gpio3_i : in std_logic; -- ext 10MHz clock input
fp_gpio4_i : in std_logic; -- ext PPS input
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- Ref clock div2 output
fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fp_gpio4_b : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
......@@ -243,7 +235,7 @@ entity wrtd_ref_svec_tdc_fd is
fmc0_tdc_led_trig4_o : out std_logic;
fmc0_tdc_led_trig5_o : out std_logic;
fmc0_prsntm2c_n_i : in std_logic;
fmc0_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
......@@ -288,7 +280,7 @@ entity wrtd_ref_svec_tdc_fd is
fmc1_fd_onewire_b : inout std_logic;
fmc1_prsntm2c_n_i : in std_logic;
fmc1_prsnt_m2c_n_i : in std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic);
......@@ -297,20 +289,6 @@ end entity wrtd_ref_svec_tdc_fd;
architecture arch of wrtd_ref_svec_tdc_fd is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
component fd_ddr_pll
port (
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
......@@ -319,49 +297,34 @@ architecture arch of wrtd_ref_svec_tdc_fd is
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 5;
constant c_NUM_WB_SLAVES : integer := 4;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_VME : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_VIC : integer := 0;
constant c_WB_SLAVE_FDL : integer := 1;
constant c_WB_SLAVE_TDC : integer := 2;
constant c_WB_SLAVE_MT : integer := 3;
constant c_WB_SLAVE_WRC : integer := 4;
constant c_WB_DESC_SYN : integer := c_NUM_WB_SLAVES;
constant c_WB_DESC_URL : integer := c_NUM_WB_SLAVES + 1;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FDL : integer := 1;
constant c_WB_SLAVE_TDC : integer := 2;
constant c_WB_SLAVE_MT : integer := 3;
constant c_TDC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0000ffff", x"00000000");
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_WB_SLAVE_FDL => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00008000"),
c_WB_SLAVE_TDC => f_sdb_embed_bridge(c_TDC_BRIDGE_SDB, x"00010000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00040000"),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
-- not really used, will be reprogrammed by software
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
0 => x"00013000", -- FMC TDC
1 => x"00018000", -- FMC Fine Delay
2 => x"00020000", -- MT Mqueue in interrupt
3 => x"00020001", -- MT Mqueue out interrupt
4 => x"00020002", -- MT Console interrupt
5 => x"00020003"); -- MT Notify interrupt
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FDL => x"0000_8000",
c_WB_SLAVE_TDC => x"0001_0000",
c_WB_SLAVE_MT => x"0002_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FDL => x"0003_fe00", -- 0x200 bytes
c_WB_SLAVE_TDC => x"0003_0000", -- 0x10000 bytes
c_WB_SLAVE_MT => x"0002_0000"); -- 0x20000 bytes
constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
(0 => x"00000000");
......@@ -424,8 +387,6 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal dcm1_clk_ref_180 : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of tdc_clk_125m : signal is "TRUE";
attribute keep of dcm1_clk_ref_0 : signal is "TRUE";
......@@ -452,10 +413,6 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
......@@ -464,13 +421,8 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal wr_led_link : std_logic;
signal wr_led_act : std_logic;
-- VIC
signal fmc_host_irq : std_logic_vector(1 downto 0);
signal mt_hmq_in_irq : std_logic;
signal mt_hmq_out_irq : std_logic;
signal mt_console_irq : std_logic;
signal mt_notify_irq : std_logic;
signal vic_master_irq : std_logic;
-- Interrupts
signal irq_vector : std_logic_vector(5 downto 0);
-- MT endpoints
signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
......@@ -522,35 +474,148 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal fmc1_fd_tdc_data_oe : std_logic;
signal fmc1_fd_owr_en, fmc1_fd_owr_in : std_logic;
signal fmc1_fd_scl_out, fmc1_fd_scl_in : std_logic;
signal fmc1_fd_sda_out, fmc1_fd_sda_in : std_logic;
signal fmc0_scl_out : std_logic;
signal fmc0_sda_out : std_logic;
attribute iob : string;
attribute iob of pps : signal is "FORCE";
begin -- architecture arch
-----------------------------------------------------------------------------
-- System reset
-----------------------------------------------------------------------------
areset_n <= vme_sysreset_n_i and rst_n_i;
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_0002", -- WRTD Node (WN) 2
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_svec_template : entity work.svec_template_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR4 => FALSE,
g_WITH_DDR5 => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 6,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 2,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION,
g_VERBOSE => FALSE)
port map (
rst_n_i => areset_n,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => tdc_clk_125m,
clk_aux_i(1) => dcm1_clk_ref_0,
clk_10m_ext_i => clk_ext_ref,
pps_ext_i => pps_ext_in,
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => pll20dac_sclk_o,
plldac_din_o => pll20dac_din_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
pcbrev_i => pcbrev_i,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => open,
irq_user_i => irq_vector,
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
pps_p_o => pps,
pps_led_o => pps_led,
link_ok_o => open,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
app_wb_o => cnx_master_out(c_WB_MASTER_VME),
app_wb_i => cnx_master_in(c_WB_MASTER_VME));
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
cmp_sdb_crossbar : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_WB_LAYOUT,
g_SDB_ADDR => c_SDB_ADDRESS)
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......@@ -559,73 +624,6 @@ begin -- architecture arch
master_i => cnx_slave_out,
master_o => cnx_slave_in);
-----------------------------------------------------------------------------
-- VME64x Core (WB Master)
-----------------------------------------------------------------------------
gen_with_vme64_core : if not g_SIM_BYPASS_VME generate
cmp_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_master_out(c_WB_MASTER_VME),
wb_i => cnx_master_in(c_WB_MASTER_VME),
int_i => vic_master_irq);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
end generate gen_with_vme64_core;
gen_without_vme64_core : if g_SIM_BYPASS_VME generate
-- synthesis translate_off
cnx_master_out(c_WB_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_master_in(c_WB_MASTER_VME);
-- synthesis translate_on
end generate gen_without_vme64_core;
cmp_vme_led_extend : gc_extend_pulse
generic map (
g_width => 5000000)
......@@ -635,29 +633,6 @@ begin -- architecture arch
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
extended_o => vme_access_led);
-----------------------------------------------------------------------------
-- Vectored Interrupt Controller (WB Slave)
-----------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map (
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_NUM_INTERRUPTS => 6,
g_INIT_VECTORS => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_host_irq(0),
irqs_i(1) => fmc_host_irq(1),
irqs_i(2) => mt_hmq_in_irq,
irqs_i(3) => mt_hmq_out_irq,
irqs_i(4) => mt_console_irq,
irqs_i(5) => mt_notify_irq,
irq_master_o => vic_master_irq);
-----------------------------------------------------------------------------
-- Mock Turtle (WB Slave)
-----------------------------------------------------------------------------
......@@ -681,10 +656,10 @@ begin -- architecture arch
host_slave_o => cnx_slave_out(c_WB_SLAVE_MT),
clk_ref_i => clk_ref_125m,
tm_i => tm,
hmq_in_irq_o => mt_hmq_in_irq,
hmq_out_irq_o => mt_hmq_out_irq,
notify_irq_o => mt_notify_irq,
console_irq_o => mt_console_irq);
hmq_in_irq_o => irq_vector(2),
hmq_out_irq_o => irq_vector(3),
notify_irq_o => irq_vector(5),
console_irq_o => irq_vector(4));
tm.cycles <= tm_cycles;
tm.tai <= tm_tai;
......@@ -730,102 +705,11 @@ begin -- architecture arch
end process p_rmq_assign;
-----------------------------------------------------------------------------
-- The WR PTP core SVEC board package (WB Slave)
-----------------------------------------------------------------------------
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_SIMULATION => g_SIMULATION,
g_VERBOSE => FALSE,
g_WITH_EXTERNAL_CLOCK_INPUT => TRUE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 2)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
clk_aux_i(0) => tdc_clk_125m,
clk_aux_i(1) => dcm1_clk_ref_0,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
pps_ext_i => pps_ext_in,
pps_p_o => pps,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act);
-- tri-state Carrier EEPROM
carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= carrier_sda_b;
carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= carrier_scl_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
carrier_onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= carrier_onewire_b;
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #1)
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
U_TDC_Core : entity work.fmc_tdc_wrapper
generic map (
g_SIMULATION => f_int2bool(g_SIMULATION),
g_WITH_DIRECT_READOUT => TRUE)
......@@ -868,10 +752,10 @@ begin -- architecture arch
tdc_led_trig3_o => fmc0_tdc_led_trig3_o,
tdc_led_trig4_o => fmc0_tdc_led_trig4_o,
tdc_led_trig5_o => fmc0_tdc_led_trig5_o,
mezz_scl_i => fmc0_scl_b,
mezz_sda_i => fmc0_sda_b,
mezz_scl_o => fmc0_scl_out,
mezz_sda_o => fmc0_sda_out,
mezz_scl_i => '0',
mezz_sda_i => '0',
mezz_scl_o => open,
mezz_sda_o => open,
mezz_one_wire_b => fmc0_tdc_one_wire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
......@@ -886,17 +770,13 @@ begin -- architecture arch
direct_slave_o => fmc_dp_wb_in(0),
slave_i => cnx_slave_in(c_WB_SLAVE_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_TDC),
irq_o => fmc_host_irq(0),
irq_o => irq_vector(0),
clk_125m_tdc_o => tdc_clk_125m);
fmc0_scl_b <= '0' when fmc0_scl_out = '0' else 'Z';
fmc0_sda_b <= '0' when fmc0_sda_out = '0' else 'Z';
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #2)
-----------------------------------------------------------------------------
cmp_fd_tdc_start1 : IBUFDS
generic map (
DIFF_TERM => TRUE,
......@@ -906,7 +786,7 @@ begin -- architecture arch
I => fmc1_fd_tdc_start_p_i,
IB => fmc1_fd_tdc_start_n_i);
U_DDR_PLL1 : fd_ddr_pll
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr1_pll_reset,
LOCKED => ddr1_pll_locked,
......@@ -918,7 +798,7 @@ begin -- architecture arch
ddr1_pll_reset <= not fmc1_fd_pll_status_i;
fmc1_fd_pll_status <= fmc1_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core : fine_delay_core
U_FineDelay_Core : entity work.fine_delay_core
generic map (
g_WITH_WR_CORE => TRUE,
g_SIMULATION => f_int2bool(g_SIMULATION),
......@@ -970,11 +850,11 @@ begin -- architecture arch
tm_dac_wr_i => tm_dac_wr(1),
owr_en_o => fmc1_fd_owr_en,
owr_i => fmc1_fd_owr_in,
i2c_scl_oen_o => fmc1_fd_scl_out,
i2c_scl_i => fmc1_fd_scl_in,
i2c_sda_oen_o => fmc1_fd_sda_out,
i2c_sda_i => fmc1_fd_sda_in,
fmc_present_n_i => fmc1_prsntm2c_n_i,
i2c_scl_oen_o => open,
i2c_scl_i => '0',
i2c_sda_oen_o => open,
i2c_sda_i => '0',
fmc_present_n_i => '0',
wb_adr_i => fmc1_mux_wb_out.adr,
wb_dat_i => fmc1_mux_wb_out.dat,
wb_dat_o => fmc1_mux_wb_in.dat,
......@@ -984,7 +864,7 @@ begin -- architecture arch
wb_we_i => fmc1_mux_wb_out.we,
wb_ack_o => fmc1_mux_wb_in.ack,
wb_stall_o => fmc1_mux_wb_in.stall,
wb_irq_o => fmc_host_irq(1));
wb_irq_o => irq_vector(1));
cmp_fmc1_wb_mux : xwb_crossbar
generic map (
......@@ -1015,11 +895,6 @@ begin -- architecture arch
fmc1_fd_onewire_b <= '0' when fmc1_fd_owr_en = '1' else 'Z';
fmc1_fd_owr_in <= fmc1_fd_onewire_b;
fmc1_scl_b <= '0' when (fmc1_fd_scl_out = '0') else 'Z';
fmc1_sda_b <= '0' when (fmc1_fd_sda_out = '0') else 'Z';
fmc1_fd_scl_in <= fmc1_scl_b;
fmc1_fd_sda_in <= fmc1_sda_b;
-----------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
-----------------------------------------------------------------------------
......@@ -1069,10 +944,10 @@ begin -- architecture arch
end process;
-- Front panel IO configuration
fp_gpio1_o <= pps;
fp_gpio2_o <= clk_ref_div2;
clk_ext_ref <= fp_gpio3_i;
pps_ext_in <= fp_gpio4_i;
fp_gpio1_b <= pps;
fp_gpio2_b <= clk_ref_div2;
clk_ext_ref <= fp_gpio3_b;
pps_ext_in <= fp_gpio4_b;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
......
software/Makefile
View file @ 7533c4d0
......@@ -10,7 +10,7 @@ REPO_PARENT ?= $(CURDIR)/..
# on Mock Turtle.
WRTD_DEP_TRTL ?= $(CURDIR)/../dependencies/mock-turtle
DIRS = $(WRTD_DEP_TRTL)/software lib firmware
DIRS = $(WRTD_DEP_TRTL)/software drivers lib firmware
all clean: $(DIRS)
......
software/drivers/Kbuild
View file @ 7533c4d0
......@@ -15,4 +15,4 @@ obj-m := wrtd-ref-spec150t-adc.o
obj-m += wrtd-ref-svec-tdc-fd.o
wrtd-ref-spec150t-adc-objs := wrtd-ref-spec150t-adc-core.o
wrtd-ref-svec-tdc-fd-objs := wrtd-ref-svec-tdc-fd-core.o
\ No newline at end of file
wrtd-ref-svec-tdc-fd-objs := wrtd-ref-svec-tdc-fd-core.o
software/firmware/adc/Makefile
View file @ 7533c4d0
......@@ -10,7 +10,7 @@ EXTRA2_CFLAGS += # To be set by user on make line
EXTRA_CFLAGS += $(EXTRA2_CFLAGS)
EXTRA_CFLAGS += -I$(CUR_DIR)/../../include
EXTRA_CFLAGS += -I$(CUR_DIR)/../common
EXTRA_CFLAGS += -I$(WRTD_DEP_FMC_ADC)/hdl/rtl/wb_gen
EXTRA_CFLAGS += -I$(WRTD_DEP_FMC_ADC)/software/include/hw
all:
......
software/firmware/adc/wrtd-adcin.c
View file @ 7533c4d0
......@@ -30,7 +30,7 @@ static inline uint32_t adcin_readl(const struct wrtd_adcin_dev *dev, uint32_t re
static inline int adcin_wr_link_up(struct wrtd_adcin_dev *adcin)
{
return adcin_readl(adcin, ALT_TRIGOUT_STATUS) & ALT_TRIGOUT_WR_LINK;
return adcin_readl(adcin, AUX_TRIGOUT_STATUS) & AUX_TRIGOUT_WR_LINK;
}
static inline int adcin_wr_time_locked(struct wrtd_adcin_dev *adcin)
......@@ -45,7 +45,7 @@ static void adcin_wr_enable_lock(struct wrtd_adcin_dev *dev, int enable)
static inline int adcin_wr_time_ready(struct wrtd_adcin_dev *adcin)
{
return adcin_readl(adcin, ALT_TRIGOUT_STATUS) & ALT_TRIGOUT_WR_VALID;
return adcin_readl(adcin, AUX_TRIGOUT_STATUS) & AUX_TRIGOUT_WR_VALID;
}
static inline int adcin_wr_sync_timeout(void)
......@@ -62,28 +62,28 @@ static inline int adcin_wr_sync_timeout(void)
*/
static void adcin_input(struct wrtd_adcin_dev *adcin)
{
uint32_t status = adcin_readl(adcin, ALT_TRIGOUT_STATUS);
uint32_t status = adcin_readl(adcin, AUX_TRIGOUT_STATUS);
uint32_t mask;
struct wrtd_event ev;
int i;
/* Poll the FIFO and read the timestamp */
if(!(status & ALT_TRIGOUT_TS_PRESENT))
if(!(status & AUX_TRIGOUT_TS_PRESENT))
return;
mask = adcin_readl(adcin, ALT_TRIGOUT_TS_MASK_SEC + 0);
ev.ts.seconds = adcin_readl(adcin, ALT_TRIGOUT_TS_MASK_SEC + 4);
ev.ts.ns = adcin_readl(adcin, ALT_TRIGOUT_TS_CYCLES) * 8;
mask = adcin_readl(adcin, AUX_TRIGOUT_TS_MASK_SEC + 0);
ev.ts.seconds = adcin_readl(adcin, AUX_TRIGOUT_TS_MASK_SEC + 4);
ev.ts.ns = adcin_readl(adcin, AUX_TRIGOUT_TS_CYCLES) * 8;
ev.ts.frac = 0;
for (i = 0; i < ADCIN_NUM_CHANNELS; i++) {
/* The last channel is the ext trigger with a different mask */
if ( i == ADCIN_NUM_CHANNELS - 1 ) {
if (!(mask & (ALT_TRIGOUT_EXT_MASK >> 32)))
if (!(mask & (AUX_TRIGOUT_EXT_MASK >> 32)))
continue;
}
else if (!(mask & ((ALT_TRIGOUT_CH1_MASK >> 32) << i)))
else if (!(mask & ((AUX_TRIGOUT_CH1_MASK >> 32) << i)))
continue;
memset(ev.id, 0, WRTD_ID_LEN);
......
software/firmware/adc/wrtd-adcout.c
View file @ 7533c4d0
......@@ -14,7 +14,7 @@
#include "mockturtle-rt.h"
#include <mockturtle-framework.h>
#include "wrtd-common.h"
#include "fmc_adc_alt_trigin.h"
#include "fmc_adc_aux_trigin.h"
#define OUT_QUEUE_MAXTIME 10
#define OUT_QUEUE_PREFIX adcout_
......@@ -91,7 +91,7 @@ static void adcout_drop_trigger(struct wrtd_adcout_dev *dev,
adcout_out_queue_pop(q);
/* Disarm the ADC output */
adcout_writel(dev, 0, ALT_TRIGIN_CTRL);
adcout_writel(dev, 0, AUX_TRIGIN_CTRL);
wrtd_log(WRTD_LOG_MSG_EV_DISCARDED, reason, NULL, ev, now);
}
......@@ -105,7 +105,7 @@ static void adcout_output (struct wrtd_adcout_dev *dev)
{
struct adcout_out_queue *q = &dev->queue;
struct wrtd_event *ev = adcout_out_queue_front(q);
uint32_t ctrl = adcout_readl(dev, ALT_TRIGIN_CTRL);
uint32_t ctrl = adcout_readl(dev, AUX_TRIGIN_CTRL);
struct wrtd_tstamp ts;
/* Check if the output has triggered */
......@@ -117,7 +117,7 @@ static void adcout_output (struct wrtd_adcout_dev *dev)
return;
}
#endif
if (ctrl & ALT_TRIGIN_CTRL_ENABLE) {
if (ctrl & AUX_TRIGIN_CTRL_ENABLE) {
/* Armed but still waiting for trigger */
struct wrtd_tstamp now;
ts_now(&now);
......@@ -147,10 +147,10 @@ static void adcout_output (struct wrtd_adcout_dev *dev)
}
/* Program the output start time */
adcout_writel(dev, 0, ALT_TRIGIN_SECONDS + 0);
adcout_writel(dev, ev->ts.seconds, ALT_TRIGIN_SECONDS + 4);
adcout_writel(dev, ev->ts.ns / 8, ALT_TRIGIN_CYCLES);
adcout_writel(dev, ALT_TRIGIN_CTRL_ENABLE, ALT_TRIGIN_CTRL);
adcout_writel(dev, 0, AUX_TRIGIN_SECONDS + 0);
adcout_writel(dev, ev->ts.seconds, AUX_TRIGIN_SECONDS + 4);
adcout_writel(dev, ev->ts.ns / 8, AUX_TRIGIN_CYCLES);
adcout_writel(dev, AUX_TRIGIN_CTRL_ENABLE, AUX_TRIGIN_CTRL);
wrtd_log(WRTD_LOG_MSG_EV_CONSUMED, WRTD_LOG_CONSUMED_START,
NULL, ev, NULL);
......
software/firmware/adc/wrtd-rt-adc.c
View file @ 7533c4d0
......@@ -9,7 +9,7 @@
#include "mockturtle-rt.h"
#include <mockturtle-framework.h>
#include "wrtd-common.h"
#include "fmc_adc_alt_trigout.h"
#include "fmc_adc_aux_trigout.h"
#define NBR_CPUS 1
#define CPU_IDX 0
......
software/lib/libwrtd.c
View file @ 7533c4d0
......@@ -20,17 +20,112 @@
* @{
*/
/**
* Retrieve the number of detected WRTD Nodes.
*
* @param[out] count number of detected WRTD Nodes
* @return #wrtd_status
*/
wrtd_status wrtd_get_node_count(uint32_t *count)
{
int i;
uint32_t dev_count = 0;
struct trtl_dev *trtl;
const struct trtl_config_rom *cfgrom;
char **dev_list = trtl_list();
if (!dev_list)
return WRTD_ERROR_INTERNAL;
for (i = 0; dev_list[i]; i++) {
trtl = trtl_open(dev_list[i]);
if (trtl == NULL) {
trtl_list_free(dev_list);
return WRTD_ERROR_RESOURCE_UNKNOWN;
}
cfgrom = trtl_config_get(trtl);
/* WRTD = 0x57525444 */
if (cfgrom->app_id == 0x57525444)
dev_count++;
trtl_close(trtl);
}
trtl_list_free(dev_list);
*count = dev_count;
return WRTD_SUCCESS;
}
/**
* Retrieve the ID of a WRTD Node.
*
* Before calling this function, you should probably call #wrtd_get_node_count to know the
* number of Nodes.
*
* @param[in] index The index of the Node ("1" for the first Node, etc.)
* @param[out] node_id The retrieved ID of the Node
* @return #wrtd_status
*/
wrtd_status wrtd_get_node_id(uint32_t index, uint32_t *node_id)
{
int i;
uint32_t dev_count = 0;
struct trtl_dev *trtl;
const struct trtl_config_rom *cfgrom;
char **dev_list = trtl_list();
if (!dev_list)
return WRTD_ERROR_INTERNAL;
*node_id = 0;
for (i = 0; dev_list[i]; i++) {
trtl = trtl_open(dev_list[i]);
if (trtl == NULL) {
trtl_list_free(dev_list);
return WRTD_ERROR_RESOURCE_UNKNOWN;
}
cfgrom = trtl_config_get(trtl);
/* WRTD = 0x57525444 */
if (cfgrom->app_id == 0x57525444)
dev_count++;
if (dev_count == index) {
char *eptr;
/* expecting string in the form of "trtl-xxxx, where
xxxx is a hex integer */
*node_id = strtoul(dev_list[i]+5, &eptr, 16);
if (*eptr != 0) {
trtl_list_free(dev_list);
trtl_close(trtl);
return WRTD_ERROR_INTERNAL;
}
}
trtl_close(trtl);
}
trtl_list_free(dev_list);
if (*node_id == 0)
return WRTD_ERROR_RESOURCE_UNKNOWN;
return WRTD_SUCCESS;
}
/**
* Initialize the WRTD Node and obtain the WRTD device token.
*
* @param[in] resource_name Underlying MockTurtle device ID in
* the form of **MTxxx** or **trtl-xxxx**.
* @param[in] node_id WRTD Node ID
* @param[in] reset Reserved for future use.
* @param[in] options_str Reserved for future use.
* @param[out] wrtd Pointer to WRTD device token.
* @return #wrtd_status
*/
wrtd_status wrtd_init(const char *resource_name,
wrtd_status wrtd_init(uint32_t node_id,
bool reset,
const char *options_str,
wrtd_dev **wrtd)
......@@ -41,35 +136,12 @@ wrtd_status wrtd_init(const char *resource_name,
struct wrtd_config_msg msg;
wrtd_status status;
static int initialized;
/* In case of error... */
*wrtd = NULL;
/* Initialize (only once).*/
if (!initialized) {
initialized = 1;
trtl_init();
}
trtl = trtl_open_by_id(node_id);
/* Resource is MTxxx where xxx is the mock-turtle device id. */
if (resource_name[0] == 'M' && resource_name[1] == 'T') {
unsigned long dev_id;
char *eptr;
dev_id = strtoul(resource_name + 2, &eptr, 0);
if (*eptr != 0) {
/* Invalid characters. */
return WRTD_ERROR_RESOURCE_UNKNOWN;
}
trtl = trtl_open_by_id(dev_id);
}
else if (strncmp(resource_name, "trtl-", 5) == 0) {
trtl = trtl_open(resource_name);
}
else {
return WRTD_ERROR_RESOURCE_UNKNOWN;
}
if (trtl == NULL)
if (trtl == NULL)
return WRTD_ERROR_RESOURCE_UNKNOWN;
wrtd_dev *res;
......@@ -666,7 +738,7 @@ wrtd_status wrtd_get_attr_int32(wrtd_dev *wrtd,
return wrtd_attr_get_stat_rule_missed_holdoff
(wrtd, rep_cap_id, value);
case WRTD_ATTR_STAT_RULE_MISSED_NOSYNC:
return wrtd_attr_get_stat_rule_missed_holdoff
return wrtd_attr_get_stat_rule_missed_nosync
(wrtd, rep_cap_id, value);
case WRTD_ATTR_STAT_RULE_MISSED_OVERFLOW:
return wrtd_attr_get_stat_rule_missed_overflow
......
software/lib/libwrtd.h
View file @ 7533c4d0
......@@ -242,7 +242,11 @@ typedef enum wrtd_attr {
/* Initialisation */
wrtd_status wrtd_init(const char *resource_name,
wrtd_status wrtd_get_node_count(uint32_t *count);
wrtd_status wrtd_get_node_id(uint32_t index, uint32_t *node_id);
wrtd_status wrtd_init(uint32_t node_id,
bool reset,
const char *options_str,
wrtd_dev **wrtd);
......
software/lib/python/PyWrtd.py
View file @ 7533c4d0
......@@ -45,11 +45,38 @@ def encode_arguments(func, *args, **kwargs):
args = tuple(encoded)
return func(*args, **kwargs)
def errcheck(ret, func, args):
"""Generic error checker for WRTD functions (with a dev token as first argument)"""
if ret < PyWrtd.WRTD_SUCCESS:
wrtd_p = args[0]
if wrtd_p:
buf_size = PyWrtd.wrtd_lib.wrtd_get_error(wrtd_p, None, 0, None)
error_description = create_string_buffer(buf_size)
PyWrtd.wrtd_lib.wrtd_get_error(wrtd_p, None,
buf_size, error_description)
msg = error_description.value.decode('ascii')
else:
error_message = create_string_buffer(256)
PyWrtd.wrtd_lib.wrtd_error_message(None, ret, error_message)
msg = error_message.value.decode('ascii')
raise OSError(ret, msg)
else:
return ret
def errcheck_static(ret, func, args):
"""Generic error checker for static WRTD functions (without a dev token)"""
if ret < PyWrtd.WRTD_SUCCESS:
error_message = create_string_buffer(256)
PyWrtd.wrtd_lib.wrtd_error_message(None, ret, error_message)
msg = error_message.value.decode('ascii')
raise OSError(ret, msg)
else:
return ret
class PyWrtd():
"""Top-level Python wrapper class for WRTD library.
:param resource_name: Underlying MockTurtle device ID in the form of ``MTxxx`` or\
``trtl-xxxx``. See also :ref:`node_id`.
:param node_id: WRTD Node ID.
"""
......@@ -127,182 +154,194 @@ class PyWrtd():
WRTD_LOG_ENTRY_SIZE = 120
def __init__(self, resource_name):
self.wrtd_lib = CDLL("libwrtd.so")
def __init__(self, node_id):
PyWrtd.ctypes_init()
self.wrtd_p = POINTER(wrtd_dev)()
ret = self.wrtd_lib.wrtd_init(node_id, 0, None, byref(self.wrtd_p))
self.wrtd_lib.wrtd_init.restype = c_int
self.wrtd_lib.wrtd_init.errcheck = self.__errcheck
self.wrtd_lib.wrtd_init.argtypes = [c_char_p, c_bool, c_char_p,
POINTER(POINTER(wrtd_dev))]
def __del__(self):
if self.wrtd_p:
self.wrtd_lib.wrtd_close(self.wrtd_p)
self.wrtd_p = 0
self.wrtd_lib.wrtd_close.restype = c_int
self.wrtd_lib.wrtd_close.errcheck = self.__errcheck
self.wrtd_lib.wrtd_close.argtypes = [POINTER(wrtd_dev)]
@staticmethod
def ctypes_init():
try:
# If already initialised, do nothing
PyWrtd.wrtd_lib
return
except AttributeError:
pass
self.wrtd_lib.wrtd_reset.restype = c_int
self.wrtd_lib.wrtd_reset.errcheck = self.__errcheck
self.wrtd_lib.wrtd_reset.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib = CDLL("libwrtd.so")
self.wrtd_lib.wrtd_get_error.restype = c_int
# No errcheck on the get_error function, it is used internally
# by self._errcheck and might lead to recursive errors
self.wrtd_lib.wrtd_get_error.argtypes = [POINTER(wrtd_dev),
POINTER(c_int),
c_int32, c_char_p]
self.wrtd_lib.wrtd_error_message.restype = c_int
self.wrtd_lib.wrtd_error_message.errcheck = self.__errcheck
self.wrtd_lib.wrtd_error_message.argtypes = [POINTER(wrtd_dev),
c_uint, c_char_p]
self.wrtd_lib.wrtd_set_attr_bool.restype = c_int
self.wrtd_lib.wrtd_set_attr_bool.errcheck = self.__errcheck
self.wrtd_lib.wrtd_set_attr_bool.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_bool]
self.wrtd_lib.wrtd_get_attr_bool.restype = c_int
self.wrtd_lib.wrtd_get_attr_bool.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_attr_bool.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, POINTER(c_bool)]
self.wrtd_lib.wrtd_set_attr_int32.restype = c_int
self.wrtd_lib.wrtd_set_attr_int32.errcheck = self.__errcheck
self.wrtd_lib.wrtd_set_attr_int32.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_int32]
self.wrtd_lib.wrtd_get_attr_int32.restype = c_int
self.wrtd_lib.wrtd_get_attr_int32.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_attr_int32.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, POINTER(c_int32)]
self.wrtd_lib.wrtd_set_attr_string.restype = c_int
self.wrtd_lib.wrtd_set_attr_string.errcheck = self.__errcheck
self.wrtd_lib.wrtd_set_attr_string.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_char_p]
PyWrtd.wrtd_lib.wrtd_get_node_count.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_node_count.errcheck = errcheck_static
PyWrtd.wrtd_lib.wrtd_get_node_count.argtypes = [POINTER(c_uint)]
self.wrtd_lib.wrtd_get_attr_string.restype = c_int
self.wrtd_lib.wrtd_get_attr_string.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_attr_string.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_get_node_id.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_node_id.errcheck = errcheck_static
PyWrtd.wrtd_lib.wrtd_get_node_id.argtypes = [c_uint, POINTER(c_uint)]
self.wrtd_lib.wrtd_set_attr_tstamp.restype = c_int
self.wrtd_lib.wrtd_set_attr_tstamp.errcheck = self.__errcheck
self.wrtd_lib.wrtd_set_attr_tstamp.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
POINTER(wrtd_tstamp)]
self.wrtd_lib.wrtd_get_attr_tstamp.restype = c_int
self.wrtd_lib.wrtd_get_attr_tstamp.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_attr_tstamp.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
POINTER(wrtd_tstamp)]
self.wrtd_lib.wrtd_clear_event_log_entries.restype = c_int
self.wrtd_lib.wrtd_clear_event_log_entries.errcheck = self.__errcheck
self.wrtd_lib.wrtd_clear_event_log_entries.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_get_next_event_log_entry.restype = c_int
self.wrtd_lib.wrtd_get_next_event_log_entry.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_next_event_log_entry.argtypes = [POINTER(wrtd_dev),
c_int32, c_char_p]
self.wrtd_lib.wrtd_add_alarm.restype = c_int
self.wrtd_lib.wrtd_add_alarm.errcheck = self.__errcheck
self.wrtd_lib.wrtd_add_alarm.argtypes = [POINTER(wrtd_dev), c_char_p]
self.wrtd_lib.wrtd_disable_all_alarms.restype = c_int
self.wrtd_lib.wrtd_disable_all_alarms.errcheck = self.__errcheck
self.wrtd_lib.wrtd_disable_all_alarms.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_remove_alarm.restype = c_int
self.wrtd_lib.wrtd_remove_alarm.errcheck = self.__errcheck
self.wrtd_lib.wrtd_remove_alarm.argtypes = [POINTER(wrtd_dev), c_char_p]
self.wrtd_lib.wrtd_remove_all_alarms.restype = c_int
self.wrtd_lib.wrtd_remove_all_alarms.errcheck = self.__errcheck
self.wrtd_lib.wrtd_remove_all_alarms.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_get_alarm_name.restype = c_int
self.wrtd_lib.wrtd_get_alarm_name.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_alarm_name.argtypes = [POINTER(wrtd_dev), c_int32,
c_int32, c_char_p]
self.wrtd_lib.wrtd_add_rule.restype = c_int
self.wrtd_lib.wrtd_add_rule.errcheck = self.__errcheck
self.wrtd_lib.wrtd_add_rule.argtypes = [POINTER(wrtd_dev), c_char_p]
self.wrtd_lib.wrtd_disable_all_rules.restype = c_int
self.wrtd_lib.wrtd_disable_all_rules.errcheck = self.__errcheck
self.wrtd_lib.wrtd_disable_all_rules.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_remove_rule.restype = c_int
self.wrtd_lib.wrtd_remove_rule.errcheck = self.__errcheck
self.wrtd_lib.wrtd_remove_rule.argtypes = [POINTER(wrtd_dev), c_char_p]
self.wrtd_lib.wrtd_remove_all_rules.restype = c_int
self.wrtd_lib.wrtd_remove_all_rules.errcheck = self.__errcheck
self.wrtd_lib.wrtd_remove_all_rules.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_get_rule_name.restype = c_int
self.wrtd_lib.wrtd_get_rule_name.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_rule_name.argtypes = [POINTER(wrtd_dev), c_int32,
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_init.restype = c_int
PyWrtd.wrtd_lib.wrtd_init.errcheck = errcheck_static
PyWrtd.wrtd_lib.wrtd_init.argtypes = [c_uint, c_bool, c_char_p,
POINTER(POINTER(wrtd_dev))]
PyWrtd.wrtd_lib.wrtd_close.restype = c_int
PyWrtd.wrtd_lib.wrtd_close.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_close.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_reset_rule_stats.restype = c_int
self.wrtd_lib.wrtd_reset_rule_stats.errcheck = self.__errcheck
self.wrtd_lib.wrtd_reset_rule_stats.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_reset.restype = c_int
PyWrtd.wrtd_lib.wrtd_reset.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_reset.argtypes = [POINTER(wrtd_dev)]
self.wrtd_lib.wrtd_get_fw_name.restype = c_int
self.wrtd_lib.wrtd_get_fw_name.errcheck = self.__errcheck
self.wrtd_lib.wrtd_get_fw_name.argtypes = [POINTER(wrtd_dev), c_int32,
PyWrtd.wrtd_lib.wrtd_get_error.restype = c_int
# No errcheck on the get_error function, it is used internally
# by errcheck and might lead to recursive errors
PyWrtd.wrtd_lib.wrtd_get_error.argtypes = [POINTER(wrtd_dev),
POINTER(c_int),
c_int32, c_char_p]
self.resource_name = resource_name.encode('utf-8')
self.wrtd_p = POINTER(wrtd_dev)()
ret = self.wrtd_lib.wrtd_init(self.resource_name, 0, None, byref(self.wrtd_p))
PyWrtd.wrtd_lib.wrtd_error_message.restype = c_int
# No errcheck on the error_message function, it is used internally
# by errcheck and might lead to recursive errors
PyWrtd.wrtd_lib.wrtd_error_message.argtypes = [POINTER(wrtd_dev),
c_uint, c_char_p]
def __del__(self):
if self.wrtd_p:
self.wrtd_lib.wrtd_close(self.wrtd_p)
self.wrtd_p = 0
PyWrtd.wrtd_lib.wrtd_set_attr_bool.restype = c_int
PyWrtd.wrtd_lib.wrtd_set_attr_bool.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_set_attr_bool.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_bool]
def reset(self):
PyWrtd.wrtd_lib.wrtd_get_attr_bool.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_attr_bool.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_attr_bool.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, POINTER(c_bool)]
PyWrtd.wrtd_lib.wrtd_set_attr_int32.restype = c_int
PyWrtd.wrtd_lib.wrtd_set_attr_int32.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_set_attr_int32.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_int32]
PyWrtd.wrtd_lib.wrtd_get_attr_int32.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_attr_int32.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_attr_int32.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, POINTER(c_int32)]
PyWrtd.wrtd_lib.wrtd_set_attr_string.restype = c_int
PyWrtd.wrtd_lib.wrtd_set_attr_string.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_set_attr_string.argtypes = [POINTER(wrtd_dev),
c_char_p,
c_uint, c_char_p]
PyWrtd.wrtd_lib.wrtd_get_attr_string.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_attr_string.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_attr_string.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_set_attr_tstamp.restype = c_int
PyWrtd.wrtd_lib.wrtd_set_attr_tstamp.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_set_attr_tstamp.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
POINTER(wrtd_tstamp)]
PyWrtd.wrtd_lib.wrtd_get_attr_tstamp.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_attr_tstamp.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_attr_tstamp.argtypes = [POINTER(wrtd_dev),
c_char_p, c_uint,
POINTER(wrtd_tstamp)]
PyWrtd.wrtd_lib.wrtd_clear_event_log_entries.restype = c_int
PyWrtd.wrtd_lib.wrtd_clear_event_log_entries.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_clear_event_log_entries.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib.wrtd_get_next_event_log_entry.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_next_event_log_entry.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_next_event_log_entry.argtypes = [POINTER(wrtd_dev),
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_add_alarm.restype = c_int
PyWrtd.wrtd_lib.wrtd_add_alarm.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_add_alarm.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_disable_all_alarms.restype = c_int
PyWrtd.wrtd_lib.wrtd_disable_all_alarms.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_disable_all_alarms.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib.wrtd_remove_alarm.restype = c_int
PyWrtd.wrtd_lib.wrtd_remove_alarm.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_remove_alarm.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_remove_all_alarms.restype = c_int
PyWrtd.wrtd_lib.wrtd_remove_all_alarms.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_remove_all_alarms.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib.wrtd_get_alarm_name.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_alarm_name.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_alarm_name.argtypes = [POINTER(wrtd_dev), c_int32,
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_add_rule.restype = c_int
PyWrtd.wrtd_lib.wrtd_add_rule.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_add_rule.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_disable_all_rules.restype = c_int
PyWrtd.wrtd_lib.wrtd_disable_all_rules.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_disable_all_rules.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib.wrtd_remove_rule.restype = c_int
PyWrtd.wrtd_lib.wrtd_remove_rule.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_remove_rule.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_remove_all_rules.restype = c_int
PyWrtd.wrtd_lib.wrtd_remove_all_rules.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_remove_all_rules.argtypes = [POINTER(wrtd_dev)]
PyWrtd.wrtd_lib.wrtd_get_rule_name.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_rule_name.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_rule_name.argtypes = [POINTER(wrtd_dev), c_int32,
c_int32, c_char_p]
PyWrtd.wrtd_lib.wrtd_reset_rule_stats.restype = c_int
PyWrtd.wrtd_lib.wrtd_reset_rule_stats.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_reset_rule_stats.argtypes = [POINTER(wrtd_dev), c_char_p]
PyWrtd.wrtd_lib.wrtd_get_fw_name.restype = c_int
PyWrtd.wrtd_lib.wrtd_get_fw_name.errcheck = errcheck
PyWrtd.wrtd_lib.wrtd_get_fw_name.argtypes = [POINTER(wrtd_dev), c_int32,
c_int32, c_char_p]
@staticmethod
def get_node_count():
"""
Corresponds to C library :cpp:func:`wrtd_reset`.
Corresponds to C library :cpp:func:`wrtd_get_node_count`.
"""
self.wrtd_lib.wrtd_reset(self.wrtd_p)
PyWrtd.ctypes_init()
count = c_uint();
PyWrtd.wrtd_lib.wrtd_get_node_count(byref(count))
return count.value;
def get_error(self):
@staticmethod
def get_node_id(index):
"""
Corresponds to C library :cpp:func:`wrtd_get_error`.
:return: a tuple with the :ref:`Error Code <api_error_codes>` and the error message.
Corresponds to C library :cpp:func:`wrtd_get_node_id`.
"""
buf_size = self.wrtd_lib.wrtd_get_error(self.wrtd_p, None, 0, None)
error_description = create_string_buffer(buf_size)
error_c = c_int()
self.wrtd_lib.wrtd_get_error(self.wrtd_p, byref(error_c),
buf_size, error_description)
return error_c.value, error_description.value.decode('ascii')
PyWrtd.ctypes_init()
node_id = c_uint();
PyWrtd.wrtd_lib.wrtd_get_node_id(index, byref(node_id))
return node_id.value;
def error_message(self, err_code):
def reset(self):
"""
Corresponds to C library :cpp:func:`wrtd_error_message`.
:param err_code: error code to convert
:return: error message (string)
Corresponds to C library :cpp:func:`wrtd_reset`.
"""
error_message = create_string_buffer(256)
self.wrtd_lib.wrtd_error_message(self.wrtd_p, err_code,
error_message)
return error_message.value.decode('ascii')
PyWrtd.wrtd_lib.wrtd_reset(self.wrtd_p)
@encode_arguments
def set_attr_bool(self, rep_cap_id, id, value):
......@@ -313,8 +352,8 @@ class PyWrtd():
:param id: ID of concerned :ref:`attribute`
:param value: Value to write to the :ref:`attribute`
"""
self.wrtd_lib.wrtd_set_attr_bool(self.wrtd_p, rep_cap_id,
id, value)
PyWrtd.wrtd_lib.wrtd_set_attr_bool(self.wrtd_p, rep_cap_id,
id, value)
@encode_arguments
def get_attr_bool(self, rep_cap_id, id):
......@@ -327,8 +366,8 @@ class PyWrtd():
:return: Retrieved attribute value
"""
value = c_bool()
self.wrtd_lib.wrtd_get_attr_bool(self.wrtd_p, rep_cap_id,
id, byref(value))
PyWrtd.wrtd_lib.wrtd_get_attr_bool(self.wrtd_p, rep_cap_id,
id, byref(value))
return value.value
@encode_arguments
......@@ -340,8 +379,8 @@ class PyWrtd():
:param id: ID of concerned :ref:`attribute`
:param value: Value to write to the :ref:`attribute`
"""
self.wrtd_lib.wrtd_set_attr_int32(self.wrtd_p, rep_cap_id,
id, value)
PyWrtd.wrtd_lib.wrtd_set_attr_int32(self.wrtd_p, rep_cap_id,
id, value)
@encode_arguments
def get_attr_int32(self, rep_cap_id, id):
......@@ -354,8 +393,8 @@ class PyWrtd():
:return: Retrieved attribute value
"""
value = c_int32()
self.wrtd_lib.wrtd_get_attr_int32(self.wrtd_p, rep_cap_id,
id, byref(value))
PyWrtd.wrtd_lib.wrtd_get_attr_int32(self.wrtd_p, rep_cap_id,
id, byref(value))
return value.value
@encode_arguments
......@@ -367,8 +406,8 @@ class PyWrtd():
:param id: ID of concerned :ref:`attribute`
:param value: Value to write to the :ref:`attribute`
"""
self.wrtd_lib.wrtd_set_attr_string(self.wrtd_p, rep_cap_id,
id, value)
PyWrtd.wrtd_lib.wrtd_set_attr_string(self.wrtd_p, rep_cap_id,
id, value)
@encode_arguments
def get_attr_string(self, rep_cap_id, id):
......@@ -380,12 +419,12 @@ class PyWrtd():
:return: Retrieved attribute value
"""
buf_size = self.wrtd_lib.wrtd_get_attr_string(self.wrtd_p,
rep_cap_id, id,
0, None)
buf_size = PyWrtd.wrtd_lib.wrtd_get_attr_string(self.wrtd_p,
rep_cap_id, id,
0, None)
value = create_string_buffer(buf_size)
self.wrtd_lib.wrtd_get_attr_string(self.wrtd_p, rep_cap_id,
id, buf_size, value)
PyWrtd.wrtd_lib.wrtd_get_attr_string(self.wrtd_p, rep_cap_id,
id, buf_size, value)
return value.value.decode('ascii')
@encode_arguments
......@@ -401,8 +440,8 @@ class PyWrtd():
:param frac: Fractional nanoseconds value to write to the :ref:`attribute`
"""
tstamp = wrtd_tstamp(seconds, ns, frac)
self.wrtd_lib.wrtd_set_attr_tstamp(self.wrtd_p, rep_cap_id,
id, byref(tstamp))
PyWrtd.wrtd_lib.wrtd_set_attr_tstamp(self.wrtd_p, rep_cap_id,
id, byref(tstamp))
@encode_arguments
def get_attr_tstamp(self, rep_cap_id, id):
......@@ -416,15 +455,15 @@ class PyWrtd():
(Python dictionary with ``seconds``, ``ns`` and ``frac`` keys)
"""
tstamp = wrtd_tstamp()
self.wrtd_lib.wrtd_get_attr_tstamp(self.wrtd_p, rep_cap_id,
id, byref(tstamp))
PyWrtd.wrtd_lib.wrtd_get_attr_tstamp(self.wrtd_p, rep_cap_id,
id, byref(tstamp))
return dict(tstamp)
def clear_event_log_entries(self):
"""
Corresponds to C library :cpp:func:`wrtd_clear_event_log_entries`.
"""
self.wrtd_lib.wrtd_clear_event_log_entries(self.wrtd_p)
PyWrtd.wrtd_lib.wrtd_clear_event_log_entries(self.wrtd_p)
def get_next_event_log_entry(self):
"""
......@@ -432,9 +471,9 @@ class PyWrtd():
"""
buf_size = self.WRTD_LOG_ENTRY_SIZE
log_entry = create_string_buffer(buf_size)
self.wrtd_lib.wrtd_get_next_event_log_entry(self.wrtd_p,
buf_size,
log_entry)
PyWrtd.wrtd_lib.wrtd_get_next_event_log_entry(self.wrtd_p,
buf_size,
log_entry)
return log_entry.value.decode('ascii')
@encode_arguments
......@@ -444,13 +483,13 @@ class PyWrtd():
:param rep_cap_id: :ref:`rep_cap_id` of new :ref:`alarm`
"""
self.wrtd_lib.wrtd_add_alarm(self.wrtd_p, rep_cap_id)
PyWrtd.wrtd_lib.wrtd_add_alarm(self.wrtd_p, rep_cap_id)
def disable_all_alarms(self):
"""
Corresponds to C library :cpp:func:`wrtd_disable_all_alarms`.
"""
self.wrtd_lib.wrtd_disable_all_alarms(self.wrtd_p)
PyWrtd.wrtd_lib.wrtd_disable_all_alarms(self.wrtd_p)
@encode_arguments
def remove_alarm(self, rep_cap_id):
......@@ -459,13 +498,13 @@ class PyWrtd():
:param rep_cap_id: :ref:`rep_cap_id` of :ref:`alarm` to remove
"""
self.wrtd_lib.wrtd_remove_alarm(self.wrtd_p, rep_cap_id)
PyWrtd.wrtd_lib.wrtd_remove_alarm(self.wrtd_p, rep_cap_id)
def remove_all_alarms(self):
"""
Corresponds to C library :cpp:func:`wrtd_remove_all_alarms`.
"""
self.wrtd_lib.wrtd_remove_all_alarms(self.wrtd_p)
PyWrtd.wrtd_lib.wrtd_remove_all_alarms(self.wrtd_p)
def get_alarm_name(self, index):
"""
......@@ -475,12 +514,12 @@ class PyWrtd():
:return: :ref:`rep_cap_id` of the :ref:`alarm`
"""
buf_size = self.wrtd_lib.wrtd_get_alarm_name(self.wrtd_p,
index,
0, None)
buf_size = PyWrtd.wrtd_lib.wrtd_get_alarm_name(self.wrtd_p,
index,
0, None)
name = create_string_buffer(buf_size)
self.wrtd_lib.wrtd_get_alarm_name(self.wrtd_p, index,
buf_size, name)
PyWrtd.wrtd_lib.wrtd_get_alarm_name(self.wrtd_p, index,
buf_size, name)
return name.value.decode('ascii')
@encode_arguments
......@@ -490,13 +529,13 @@ class PyWrtd():
:param rep_cap_id: :ref:`rep_cap_id` of new :ref:`rule`
"""
self.wrtd_lib.wrtd_add_rule(self.wrtd_p, rep_cap_id)
PyWrtd.wrtd_lib.wrtd_add_rule(self.wrtd_p, rep_cap_id)
def disable_all_rules(self):
"""
Corresponds to C library :cpp:func:`wrtd_disable_all_alarms`.
"""
self.wrtd_lib.wrtd_disable_all_rules(self.wrtd_p)
PyWrtd.wrtd_lib.wrtd_disable_all_rules(self.wrtd_p)
@encode_arguments
def remove_rule(self, rep_cap_id):
......@@ -505,13 +544,13 @@ class PyWrtd():
:param rep_cap_id: :ref:`rep_cap_id` of :ref:`rule` to remove
"""
self.wrtd_lib.wrtd_remove_rule(self.wrtd_p, rep_cap_id)
PyWrtd.wrtd_lib.wrtd_remove_rule(self.wrtd_p, rep_cap_id)
def remove_all_rules(self):
"""
Corresponds to C library :cpp:func:`wrtd_remove_all_rules`.
"""
self.wrtd_lib.wrtd_remove_all_rules(self.wrtd_p)
PyWrtd.wrtd_lib.wrtd_remove_all_rules(self.wrtd_p)
def get_rule_name(self, index):
"""
......@@ -521,12 +560,12 @@ class PyWrtd():
:return: :ref:`rep_cap_id` of the :ref:`rule`
"""
buf_size = self.wrtd_lib.wrtd_get_rule_name(self.wrtd_p,
index,
0, None)
buf_size = PyWrtd.wrtd_lib.wrtd_get_rule_name(self.wrtd_p,
index,
0, None)
name = create_string_buffer(buf_size)
self.wrtd_lib.wrtd_get_rule_name(self.wrtd_p, index,
buf_size, name)
PyWrtd.wrtd_lib.wrtd_get_rule_name(self.wrtd_p, index,
buf_size, name)
return name.value.decode('ascii')
@encode_arguments
......@@ -536,7 +575,7 @@ class PyWrtd():
:param rep_cap_id: :ref:`rep_cap_id` of the :ref:`rule` to reset its statistics
"""
self.wrtd_lib.wrtd_reset_rule_stats(self.wrtd_p, rep_cap_id)
PyWrtd.wrtd_lib.wrtd_reset_rule_stats(self.wrtd_p, rep_cap_id)
def get_fw_name(self, index):
"""
......@@ -546,21 +585,10 @@ class PyWrtd():
:return: :ref:`rep_cap_id` of the :ref:`application`
"""
buf_size = self.wrtd_lib.wrtd_get_fw_name(self.wrtd_p,
index,
0, None)
buf_size = PyWrtd.wrtd_lib.wrtd_get_fw_name(self.wrtd_p,
index,
0, None)
name = create_string_buffer(buf_size)
self.wrtd_lib.wrtd_get_fw_name(self.wrtd_p, index,
buf_size, name)
PyWrtd.wrtd_lib.wrtd_get_fw_name(self.wrtd_p, index,
buf_size, name)
return name.value.decode('ascii')
def __errcheck(self, ret, func, args):
"""Generic error checker for WRTD functions"""
if ret < self.WRTD_SUCCESS:
if self.wrtd_p:
code, msg = self.get_error()
else:
code, msg = ret, self.error_message(ret)
raise OSError(ret, 'Error {0}: {1}'.format(hex(code% (1 << 32)), msg))
else:
return ret
software/tools/.gitignore deleted 100644 → 0
View file @ 0c081bed
wrtd-boot
wrtd-in-config
wrtd-out-config
wrtd-logging
wrtd-config
software/tools/wrtd-logging.py deleted 100644 → 0
View file @ 0c081bed
"""
@file wrtd-logging.py
@copyright: Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: LGPL-3.0-or-later
"""
import sys
import signal
import argparse
from PyWrtd import *
def signal_handler(sig, frame):
sys.exit(0)
def print_logging(wrtd, count):
n_read = 0
while ((count == 0) or (n_read < count)):
log_entry = wrtd.get_next_event_log_entry()
if len(log_entry):
print(log_entry)
n_read += 1
def main():
signal.signal(signal.SIGINT, signal_handler)
parser = argparse.ArgumentParser(description='WRTD node log monitoring tool')
parser.add_argument('-D', '--dev-id', dest='dev', required=True, type=int,
help='MockTurtle device ID (integer) to open')
parser.add_argument('-c', '--count', dest='count', type=int, default=0,
help='Number of entries to read (0 = infinite)')
parser.add_argument('-e', '--enable', action='store_true',
help='Enable event logging on the Node if not already enabled.')
args = parser.parse_args()
dev = 'MT' + str(args.dev)
wrtd = PyWrtd(dev)
if (args.enable):
wrtd.set_attr_bool(PyWrtd.WRTD_GLOBAL_REP_CAP_ID,
PyWrtd.WRTD_ATTR_EVENT_LOG_ENABLED,
True)
print_logging(wrtd, args.count)
if __name__ == "__main__":
main()
software/tools/wrtd-config.py → software/tools/wrtd-tool.py
View file @ 7533c4d0
"""
@file wrtd-config.py
@file wrtd-tool.py
@copyright: Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: LGPL-3.0-or-later
"""
import sys
import signal
import time
import argparse
import re
from PyWrtd import *
def signal_handler(sig, frame):
sys.exit(0)
def __tstamp_normalise(tstamp):
ret = tstamp
while (ret['ns'] >= 1000000000):
......@@ -36,6 +41,16 @@ def __tstamp_to_str(tstamp):
int(ret['ns'] / 1e1) % 1000,
ret['frac'] >> (32 - 9))
def cmd_list_nodes(args):
for i in range((PyWrtd.get_node_count())):
node_id = PyWrtd.get_node_id(i+1)
print('-> WRTD Node detected with ID: {0}'.format(node_id))
if args.verbose:
wrtd = PyWrtd(node_id)
args.verbose = False
cmd_sys_info(wrtd, args)
args.verbose = True
def cmd_sys_info(wrtd, args):
print('')
cmd_sys_time(wrtd, args)
......@@ -82,7 +97,20 @@ def cmd_sys_time(wrtd, args):
def cmd_set_log(wrtd, args):
wrtd.set_attr_bool(wrtd.WRTD_GLOBAL_REP_CAP_ID,
wrtd.WRTD_ATTR_EVENT_LOG_ENABLED,
args.log == "on")
args.set_log == True)
def cmd_show_log(wrtd, args):
if (args.set_log):
cmd_set_log(wrtd, args)
n_read = 0
while ((args.count == 0) or (n_read < args.count)):
log_entry = wrtd.get_next_event_log_entry()
if len(log_entry):
print(log_entry)
n_read += 1
def cmd_clear_log(wrtd, args):
wrtd.clear_event_log_entries()
......@@ -279,47 +307,83 @@ def time_interval_help():
def main():
parser = argparse.ArgumentParser(description='WRTD node configuration tool')
parser.add_argument('-D', '--dev-id', dest='dev', required=True, type=int,
help='MockTurtle device ID (integer) to open')
parser = argparse.ArgumentParser(description='WRTD Node configuration tool')
devid_parse = argparse.ArgumentParser(add_help=False)
devid_parse.add_argument('devid', type=lambda x: int(x,0),
metavar='<node_id>',
help='The ID of the WRTD Node (int, can be hex with "0x" prefix)')
verbose_parse = argparse.ArgumentParser(add_help=False)
verbose_parse.add_argument('-v', '--verbose', action='store_true',
help='Show more details')
rname_parse = argparse.ArgumentParser(add_help=False)
rname_parse.add_argument('name', metavar='<rule_id>',
help='The ID of the Rule (string up to 15 characters)')
aname_parse = argparse.ArgumentParser(add_help=False)
aname_parse.add_argument('name', metavar='<alarm_id>',
help='The ID of the Alarm (string up to 15 characters)')
subparsers = parser.add_subparsers(title='Available commands',
dest='command', metavar='<command>',
help='(Use "<command> -h" to get more details)')
subparsers.required = True;
# list-nodes
cmd_parser = subparsers.add_parser('list-nodes',
help='List the IDs of all detected WRTD Nodes',
parents=[verbose_parse])
cmd_parser.set_defaults(func=cmd_list_nodes, devid=None)
# sys-info
cmd_parser = subparsers.add_parser('sys-info', help='Show system information')
cmd_parser.add_argument('-v', '--verbose', action='store_true',
help='Show more details')
cmd_parser = subparsers.add_parser('sys-info', help='Show system information',
parents=[devid_parse, verbose_parse])
cmd_parser.set_defaults(func=cmd_sys_info)
# sys-time
cmd_parser = subparsers.add_parser('sys-time', help='Show current system time')
cmd_parser = subparsers.add_parser('sys-time', help='Show current system time',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_sys_time)
# set-log
cmd_parser = subparsers.add_parser('set-log', help='Enable/Disable logging')
cmd_parser.add_argument('log', choices=['on', 'off'], help='Enable/Disable logging')
cmd_parser.set_defaults(func=cmd_set_log)
# enable-log
cmd_parser = subparsers.add_parser('enable-log', help='Enable logging',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_set_log, set_log=True)
# disable-log
cmd_parser = subparsers.add_parser('disable-log', help='Disable logging',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_set_log, set_log=False)
# show-log
cmd_parser = subparsers.add_parser('show-log', help='Show log entries',
parents=[devid_parse])
cmd_parser.add_argument('-c', '--count', dest='count', type=int, default=0,
help='Number of entries to read (0 = infinite, the default)')
cmd_parser.add_argument('-e', '--enable', dest='set_log', action='store_true',
help='Enable event logging on the Node if not already enabled')
cmd_parser.set_defaults(func=cmd_show_log)
# clear-log
cmd_parser = subparsers.add_parser('clear-log', help='Clear pending log entries')
cmd_parser = subparsers.add_parser('clear-log', help='Clear pending log entries',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_clear_log)
# list-rules
cmd_parser = subparsers.add_parser('list-rules', help='List all defined Rules')
cmd_parser.add_argument('-v', '--verbose', action='store_true',
help='Show details about each Rule')
cmd_parser = subparsers.add_parser('list-rules', help='List all defined Rules',
parents=[devid_parse, verbose_parse])
cmd_parser.set_defaults(func=cmd_list_rules)
# add-rule
cmd_parser = subparsers.add_parser('add-rule', help='Define a new Rule')
cmd_parser.add_argument('name', help='The name of the new Rule')
cmd_parser = subparsers.add_parser('add-rule', help='Define a new Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_add_rule)
# set-rule
cmd_parser = subparsers.add_parser('set-rule', help='Configure a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to configure')
cmd_parser = subparsers.add_parser('set-rule', help='Configure a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.add_argument('-d', '--delay', type=time_interval, default = 0,
help='Set the delay for this Rule. ' + time_interval_help())
cmd_parser.add_argument('source', help='The source Event ID for this Rule.')
......@@ -327,53 +391,53 @@ def main():
cmd_parser.set_defaults(func=cmd_set_rule)
# remove-rule
cmd_parser = subparsers.add_parser('remove-rule', help='Delete a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to delete')
cmd_parser = subparsers.add_parser('remove-rule', help='Delete a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_remove_rule)
# remove-all-rules
cmd_parser = subparsers.add_parser('remove-all-rules', help='Delete all Rules')
cmd_parser = subparsers.add_parser('remove-all-rules', help='Delete all Rules',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_remove_all_rules)
# enable-rule
cmd_parser = subparsers.add_parser('enable-rule', help='Enable a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to enable')
cmd_parser = subparsers.add_parser('enable-rule', help='Enable a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_enable_rule)
# disable-rule
cmd_parser = subparsers.add_parser('disable-rule', help='Disable a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to disable')
cmd_parser = subparsers.add_parser('disable-rule', help='Disable a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_disable_rule)
# disable-all-rules
cmd_parser = subparsers.add_parser('disable-all-rules', help='Disable all Rules')
cmd_parser = subparsers.add_parser('disable-all-rules', help='Disable all Rules',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_disable_all_rules)
# rule-info
cmd_parser = subparsers.add_parser('rule-info', help='Display information about a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to display its information')
cmd_parser = subparsers.add_parser('rule-info', help='Display information about a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_rule_info)
# reset-rule-stats
cmd_parser = subparsers.add_parser('reset-rule-stats', help='Reset all statistics of a Rule')
cmd_parser.add_argument('name', help='The name of the Rule to reset its statistics')
cmd_parser = subparsers.add_parser('reset-rule-stats', help='Reset all statistics of a Rule',
parents=[devid_parse, rname_parse])
cmd_parser.set_defaults(func=cmd_reset_rule_stats)
# list-alarms
cmd_parser = subparsers.add_parser('list-alarms', help='List all defined Alarms')
cmd_parser.add_argument('-v', '--verbose', action='store_true',
help='Show details about each Alarm')
cmd_parser = subparsers.add_parser('list-alarms', help='List all defined Alarms',
parents=[devid_parse, verbose_parse])
cmd_parser.set_defaults(func=cmd_list_alarms)
# add-alarm
cmd_parser = subparsers.add_parser('add-alarm', help='Define a new Alarm')
cmd_parser.add_argument('name', help='The name of the new Alarm')
cmd_parser = subparsers.add_parser('add-alarm', help='Define a new Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.set_defaults(func=cmd_add_alarm)
# set-alarm
cmd_parser = subparsers.add_parser('set-alarm', help='Configure an Alarm')
cmd_parser.add_argument('name', help='The name of the Alarm to configure')
cmd_parser = subparsers.add_parser('set-alarm', help='Configure an Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.add_argument('-d', '--delay', type=time_interval, required = True,
help='Set the delay for this Alarm wrt now. ' + time_interval_help())
cmd_parser.add_argument('-s', '--setup', type=time_interval, default = 0,
......@@ -387,40 +451,43 @@ def main():
cmd_parser.set_defaults(func=cmd_set_alarm)
# remove-alarm
cmd_parser = subparsers.add_parser('remove-alarm', help='Delete an Alarm')
cmd_parser.add_argument('name', help='The name of the Alarm to delete')
cmd_parser = subparsers.add_parser('remove-alarm', help='Delete an Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.set_defaults(func=cmd_remove_alarm)
# remove-all-alarms
cmd_parser = subparsers.add_parser('remove-all-alarms', help='Delete all Alarms')
cmd_parser = subparsers.add_parser('remove-all-alarms', help='Delete all Alarms',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_remove_all_alarms)
# enable-alarm
cmd_parser = subparsers.add_parser('enable-alarm', help='Enable an Alarm')
cmd_parser.add_argument('name', help='The name of the Alarm to enable')
cmd_parser = subparsers.add_parser('enable-alarm', help='Enable an Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.set_defaults(func=cmd_enable_alarm)
# disable-alarm
cmd_parser = subparsers.add_parser('disable-alarm', help='Disable an Alarm')
cmd_parser.add_argument('name', help='The name of the Alarm to disable')
cmd_parser = subparsers.add_parser('disable-alarm', help='Disable an Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.set_defaults(func=cmd_disable_alarm)
# disable-all-alarms
cmd_parser = subparsers.add_parser('disable-all-alarms', help='Disable all Alarms')
cmd_parser = subparsers.add_parser('disable-all-alarms', help='Disable all Alarms',
parents=[devid_parse])
cmd_parser.set_defaults(func=cmd_disable_all_alarms)
# alarm-info
cmd_parser = subparsers.add_parser('alarm-info', help='Display information about an Alarm')
cmd_parser.add_argument('name', help='The name of the Alarm to display its information')
cmd_parser = subparsers.add_parser('alarm-info', help='Display information about an Alarm',
parents=[devid_parse, aname_parse])
cmd_parser.set_defaults(func=cmd_alarm_info)
args = parser.parse_args()
dev = 'MT' + str(args.dev)
wrtd = PyWrtd(dev)
args.func(wrtd, args)
if (args.devid != None):
wrtd = PyWrtd(args.devid)
args.func(wrtd, args)
else:
args.func(args)
if __name__ == "__main__":
signal.signal(signal.SIGINT, signal_handler)
main()
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