Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Trigger Distribution
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Trigger Distribution
Commits
76323b46
Commit
76323b46
authored
Jan 16, 2019
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Remove old fmc-adc-100m14b4cha directory.
parent
a41a7470
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
0 additions
and
701 deletions
+0
-701
config.yaml
builder/fmc-adc-100m14b4cha/config.yaml
+0
-7
repo.txt
builder/fmc-adc-100m14b4cha/repo.txt
+0
-1
svec-fmc0.ucf
builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
+0
-216
svec-fmc1.ucf
builder/fmc-adc-100m14b4cha/svec-fmc1.ucf
+0
-49
top.vhd
builder/fmc-adc-100m14b4cha/top.vhd
+0
-428
No files found.
builder/fmc-adc-100m14b4cha/config.yaml
deleted
100644 → 0
View file @
a41a7470
repo
:
"
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
bus
:
input
:
"
wb_adc{n}_trigin_slave"
output
:
"
wb_adc{n}_trigout_slave"
builder/fmc-adc-100m14b4cha/repo.txt
deleted
100644 → 0
View file @
a41a7470
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
deleted
100644 → 0
View file @
a41a7470
# DDR0 (bank 4)
NET "ddr0_rzq_b" LOC = L7;
NET "ddr0_we_n_o" LOC = F4;
NET "ddr0_udqs_p_b" LOC = K2;
NET "ddr0_udqs_n_b" LOC = K1;
NET "ddr0_udm_o" LOC = K4;
NET "ddr0_reset_n_o" LOC = G5;
NET "ddr0_ras_n_o" LOC = C1;
NET "ddr0_odt_o" LOC = E4;
NET "ddr0_ldqs_p_b" LOC = J5;
NET "ddr0_ldqs_n_b" LOC = J4;
NET "ddr0_ldm_o" LOC = K3;
NET "ddr0_cke_o" LOC = C4;
NET "ddr0_ck_p_o" LOC = E3;
NET "ddr0_ck_n_o" LOC = E1;
NET "ddr0_cas_n_o" LOC = B1;
NET "ddr0_dq_b[15]" LOC = M1;
NET "ddr0_dq_b[14]" LOC = M2;
NET "ddr0_dq_b[13]" LOC = L1;
NET "ddr0_dq_b[12]" LOC = L3;
NET "ddr0_dq_b[11]" LOC = L4;
NET "ddr0_dq_b[10]" LOC = L5;
NET "ddr0_dq_b[9]" LOC = M3;
NET "ddr0_dq_b[8]" LOC = M4;
NET "ddr0_dq_b[7]" LOC = H1;
NET "ddr0_dq_b[6]" LOC = H2;
NET "ddr0_dq_b[5]" LOC = G1;
NET "ddr0_dq_b[4]" LOC = G3;
NET "ddr0_dq_b[3]" LOC = J1;
NET "ddr0_dq_b[2]" LOC = J3;
NET "ddr0_dq_b[1]" LOC = H3;
NET "ddr0_dq_b[0]" LOC = H4;
NET "ddr0_ba_o[2]" LOC = F3;
NET "ddr0_ba_o[1]" LOC = D1;
NET "ddr0_ba_o[0]" LOC = D2;
NET "ddr0_a_o[13]" LOC = B5;
NET "ddr0_a_o[12]" LOC = A4;
NET "ddr0_a_o[11]" LOC = G4;
NET "ddr0_a_o[10]" LOC = D5;
NET "ddr0_a_o[9]" LOC = A2;
NET "ddr0_a_o[8]" LOC = B2;
NET "ddr0_a_o[7]" LOC = B3;
NET "ddr0_a_o[6]" LOC = F1;
NET "ddr0_a_o[5]" LOC = F2;
NET "ddr0_a_o[4]" LOC = C5;
NET "ddr0_a_o[3]" LOC = E5;
NET "ddr0_a_o[2]" LOC = A3;
NET "ddr0_a_o[1]" LOC = D3;
NET "ddr0_a_o[0]" LOC = D4;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
# FMC0
NET "fmc0_adc_ext_trigger_n_i" LOC = "A15";
NET "fmc0_adc_ext_trigger_p_i" LOC = "B15";
NET "fmc0_adc_dco_n_i" LOC = "A16";
NET "fmc0_adc_dco_p_i" LOC = "C16";
NET "fmc0_adc_fr_n_i" LOC = "G21";
NET "fmc0_adc_fr_p_i" LOC = "H21";
NET "fmc0_adc_outa_n_i[0]" LOC = "E17";
NET "fmc0_adc_outa_p_i[0]" LOC = "F17";
NET "fmc0_adc_outb_n_i[0]" LOC = "G16";
NET "fmc0_adc_outb_p_i[0]" LOC = "H16";
NET "fmc0_adc_outa_n_i[1]" LOC = "E19";
NET "fmc0_adc_outa_p_i[1]" LOC = "F19";
NET "fmc0_adc_outb_n_i[1]" LOC = "F18";
NET "fmc0_adc_outb_p_i[1]" LOC = "G18";
NET "fmc0_adc_outa_n_i[2]" LOC = "K21";
NET "fmc0_adc_outa_p_i[2]" LOC = "L21";
NET "fmc0_adc_outb_n_i[2]" LOC = "L20";
NET "fmc0_adc_outb_p_i[2]" LOC = "M20";
NET "fmc0_adc_outa_n_i[3]" LOC = "F22";
NET "fmc0_adc_outa_p_i[3]" LOC = "G22";
NET "fmc0_adc_outb_n_i[3]" LOC = "L19";
NET "fmc0_adc_outb_p_i[3]" LOC = "M19";
NET "fmc0_adc_spi_din_i" LOC = "F11";
NET "fmc0_adc_spi_dout_o" LOC = "K11";
NET "fmc0_adc_spi_sck_o" LOC = "L11";
NET "fmc0_adc_spi_cs_adc_n_o" LOC = "J13";
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = "H11";
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = "G11";
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = "J12";
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = "H12";
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = "H13";
NET "fmc0_adc_gpio_led_acq_o" LOC = "K12";
NET "fmc0_adc_gpio_led_trig_o" LOC = "L12";
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "fmc0_adc_gpio_si570_oe_o" LOC = "A25";
NET "fmc0_adc_si570_scl_b" LOC = "H14";
NET "fmc0_adc_si570_sda_b" LOC = "J14";
NET "fmc0_adc_one_wire_b" LOC = "E9";
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "rst_ddr_333m_n" TPTHRU = ddr0_rst;
TIMESPEC TS_ddr0_rst_tig = FROM FFS THRU ddr0_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "cmp_ddr0_ctrl_bank/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank4_clk;
TIMEGRP "ddr0_clk" = "ddr_clk_333m" "ddr_bank4_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_reg = FROM ddr0_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
builder/fmc-adc-100m14b4cha/svec-fmc1.ucf
deleted
100644 → 0
View file @
a41a7470
# DDR1 (bank 5)
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
NET "ddr_udqs_n_b[1]" LOC = K30;
NET "ddr_udm_o[1]" LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]" LOC = K26;
NET "ddr_odt_o[1]" LOC = E30;
NET "ddr_ldqs_p_b[1]" LOC = J29;
NET "ddr_ldqs_n_b[1]" LOC = J30;
NET "ddr_ldm_o[1]" LOC = J28;
NET "ddr_cke_o[1]" LOC = B29;
NET "ddr_ck_p_o[1]" LOC = E27;
NET "ddr_ck_n_o[1]" LOC = E28;
NET "ddr_cas_n_o[1]" LOC = K27;
NET "ddr_dq_b[31]" LOC = M30;
NET "ddr_dq_b[30]" LOC = M28;
NET "ddr_dq_b[29]" LOC = M27;
NET "ddr_dq_b[28]" LOC = M26;
NET "ddr_dq_b[27]" LOC = L30;
NET "ddr_dq_b[26]" LOC = L29;
NET "ddr_dq_b[25]" LOC = L28;
NET "ddr_dq_b[24]" LOC = L27;
NET "ddr_dq_b[23]" LOC = F30;
NET "ddr_dq_b[22]" LOC = F28;
NET "ddr_dq_b[21]" LOC = G28;
NET "ddr_dq_b[20]" LOC = G27;
NET "ddr_dq_b[19]" LOC = G30;
NET "ddr_dq_b[18]" LOC = G29;
NET "ddr_dq_b[17]" LOC = H30;
NET "ddr_dq_b[16]" LOC = H28;
NET "ddr_ba_o[5]" LOC = D26;
NET "ddr_ba_o[4]" LOC = C27;
NET "ddr_ba_o[3]" LOC = D27;
NET "ddr_a_o[27]" LOC = A28;
NET "ddr_a_o[26]" LOC = B30;
NET "ddr_a_o[25]" LOC = A26;
NET "ddr_a_o[24]" LOC = F26;
NET "ddr_a_o[23]" LOC = A27;
NET "ddr_a_o[22]" LOC = B27;
NET "ddr_a_o[21]" LOC = C29;
NET "ddr_a_o[20]" LOC = H27;
NET "ddr_a_o[19]" LOC = H26;
NET "ddr_a_o[18]" LOC = F27;
NET "ddr_a_o[17]" LOC = E29;
NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
builder/fmc-adc-100m14b4cha/top.vhd
deleted
100644 → 0
View file @
a41a7470
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment