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White Rabbit Trigger Distribution
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White Rabbit Trigger Distribution
Commits
806ca89c
Commit
806ca89c
authored
Aug 01, 2018
by
Dimitris Lampridis
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hdl/syn: embed Xilinx project options to Manifest
parent
7b1a5c27
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3 changed files
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34 additions
and
4 deletions
+34
-4
.gitignore
hdl/syn/svec/list_tdc_fd/.gitignore
+1
-0
Manifest.py
hdl/syn/svec/list_tdc_fd/Manifest.py
+7
-4
syn_extra_steps.tcl
hdl/syn/svec/list_tdc_fd/syn_extra_steps.tcl
+26
-0
No files found.
hdl/syn/svec/list_tdc_fd/.gitignore
View file @
806ca89c
...
@@ -2,3 +2,4 @@
...
@@ -2,3 +2,4 @@
!.gitignore
!.gitignore
!Manifest.py
!Manifest.py
!*.ucf
!*.ucf
!syn_extra_steps.tcl
hdl/syn/svec/list_tdc_fd/Manifest.py
View file @
806ca89c
...
@@ -12,13 +12,16 @@ syn_grade = "-3"
...
@@ -12,13 +12,16 @@ syn_grade = "-3"
syn_package
=
"fgg900"
syn_package
=
"fgg900"
syn_top
=
"svec_list_top"
syn_top
=
"svec_list_top"
syn_project
=
"svec_list_tdc_fd.xise"
syn_project
=
"svec_list_tdc_fd.xise"
syn_tool
=
"ise"
syn_tool
=
"ise"
fetchto
=
"../../../../dependencies"
fetchto
=
"../../../../dependencies"
syn_post_project_cmd
=
"$(TCL_INTERPRETER) "
+
\
syn_post_project_cmd
=
(
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
"$(TCL_INTERPRETER) "
+
\
syn_tool
+
" $(PROJECT_FILE)"
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files
=
[
files
=
[
"svec_list_top.ucf"
,
"svec_list_top.ucf"
,
...
...
hdl/syn/svec/list_tdc_fd/syn_extra_steps.tcl
0 → 100644
View file @
806ca89c
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
#xilinx::project set "Register Balancing" "Yes"
xilinx::project set
"Register Duplication Map"
"On"
xilinx::project save
xilinx::project close
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