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White Rabbit Trigger Distribution
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935b67b0
Commit
935b67b0
authored
Jul 17, 2019
by
Dimitris Lampridis
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[hdl] update wrtd_ref_spec150t_adc to use buildinfo and remove sdb from top level crossbar
parent
0aa922c4
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4 changed files
with
35 additions
and
55 deletions
+35
-55
spec
dependencies/spec
+1
-1
Manifest.py
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
+15
-15
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+5
-5
wrtd_ref_spec150t_adc.vhd
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+14
-34
No files found.
spec
@
0202f6c2
Subproject commit 0
0b12ec7cca6d304b0e2646fa5af66cd896d3aa9
Subproject commit 0
202f6c2f023bfcb3f7d7a3a420e0ec17f56f79f
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @
935b67b0
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board
=
"spec"
target
=
"xilinx"
action
=
"synthesis"
...
...
@@ -14,21 +9,16 @@ syn_top = "wrtd_ref_spec150t_adc"
syn_project
=
"wrtd_ref_spec150t_adc.xise"
syn_tool
=
"ise"
fetchto
=
"../../../dependencies"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../../dependencies"
ctrls
=
[
"bank3_64b_32b"
]
syn_pre_project_cmd
=
"make -C ../../../software/firmware"
syn_post_project_cmd
=
(
"$(TCL_INTERPRETER) "
+
\
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files
=
[
"wrtd_ref_spec150t_adc.ucf"
,
"buildinfo_pkg.vhd"
,
]
modules
=
{
...
...
@@ -36,3 +26,13 @@ modules = {
"../../top/wrtd_ref_spec150t_adc"
,
],
}
syn_pre_project_cmd
=
"make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @
935b67b0
...
...
@@ -479,10 +479,10 @@ TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "*
/
cmp_ddr_ctrl_bank3/*/c?_pll_lock" TIG;
NET "*
/
cmp_ddr_ctrl_bank3/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*
/
cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "*
/
cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "*cmp_ddr_ctrl_bank3/*/c?_pll_lock" TIG;
NET "*cmp_ddr_ctrl_bank3/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
...
...
@@ -498,7 +498,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "*
/
cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
...
...
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @
935b67b0
...
...
@@ -35,7 +35,6 @@ use work.gencores_pkg.all;
use
work
.
wishbone_pkg
.
all
;
use
work
.
mt_mqueue_pkg
.
all
;
use
work
.
mock_turtle_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
...
...
@@ -220,40 +219,22 @@ architecture arch of wrtd_ref_spec150t_adc is
constant
c_WB_SLAVE_METADATA
:
integer
:
=
0
;
constant
c_WB_SLAVE_FMC_ADC
:
integer
:
=
1
;
constant
c_WB_SLAVE_MT
:
integer
:
=
2
;
constant
c_WB_DESC_SYN
:
integer
:
=
c_NUM_WB_SLAVES
+
0
;
constant
c_WB_DESC_URL
:
integer
:
=
c_NUM_WB_SLAVES
+
1
;
-- sdb header address on primary crossbar
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00040000"
;
-- Convertion metadata base address
constant
c_METADATA_ADDR
:
t_wishbone_address
:
=
x"0000_2000"
;
constant
c_WB_METADATA_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_SDB_ENDIAN_BIG
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"0000000000001FFF"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000603"
,
version
=>
x"00000001"
,
date
=>
x"20190710"
,
name
=>
"WB-METADATA "
)));
constant
c_FMC_BRIDGE_SDB
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"00001fff"
,
x"00000000"
);
-- Primary wishbone crossbar layout
constant
c_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
+
1
downto
0
)
:
=
(
c_WB_SLAVE_METADATA
=>
f_sdb_embed_device
(
c_WB_METADATA_SDB
,
c_METADATA_ADDR
),
c_WB_SLAVE_FMC_ADC
=>
f_sdb_embed_bridge
(
c_FMC_BRIDGE_SDB
,
x"0000_4000"
),
c_WB_SLAVE_MT
=>
f_sdb_embed_device
(
c_MOCK_TURTLE_SDB
,
x"0002_0000"
),
c_WB_DESC_SYN
=>
f_sdb_embed_synthesis
(
c_SDB_SYNTHESIS_INFO
),
c_WB_DESC_URL
=>
f_sdb_embed_repo_url
(
c_SDB_REPO_URL
));
constant
c_WB_LAYOUT_ADDR
:
t_wishbone_address_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
c_WB_SLAVE_METADATA
=>
c_METADATA_ADDR
,
c_WB_SLAVE_FMC_ADC
=>
x"0000_4000"
,
c_WB_SLAVE_MT
=>
x"0002_0000"
);
constant
c_WB_LAYOUT_MASK
:
t_wishbone_address_array
(
c_NUM_WB_SLAVES
-
1
downto
0
)
:
=
(
c_WB_SLAVE_METADATA
=>
x"0003_e000"
,
c_WB_SLAVE_FMC_ADC
=>
x"0003_e000"
,
c_WB_SLAVE_MT
=>
x"0002_0000"
);
constant
c_MT_CONFIG
:
t_mt_config
:
=
(
...
...
@@ -494,15 +475,14 @@ begin -- architecture arch
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_
sdb_crossbar
:
xwb_sd
b_crossbar
cmp_
crossbar
:
xw
b_crossbar
generic
map
(
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
c_NUM_WB_MASTERS
,
g_NUM_SLAVES
=>
c_NUM_WB_SLAVES
,
g_REGISTERED
=>
TRUE
,
g_WRAPAROUND
=>
TRUE
,
g_LAYOUT
=>
c_WB_LAYOUT
,
g_SDB_ADDR
=>
c_SDB_ADDRESS
)
g_ADDRESS
=>
c_WB_LAYOUT_ADDR
,
g_MASK
=>
c_WB_LAYOUT_MASK
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
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