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White Rabbit Trigger Distribution
Commit 9652761d authored by Tristan Gingold's avatar Tristan Gingold
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Adjust various parts so that the design can be analyzed.

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general-cores @ 0545c25b
Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
wr-cores @ 2573b6cd
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07 Subproject commit 2573b6cd58732813593e12e3144ff8c87955228c
hdl/top/svec/list_tdc_fd/svec_top.vhd
View file @ 9652761d
...@@ -6,11 +6,11 @@ ...@@ -6,11 +6,11 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2014-04-01 -- Created : 2014-04-01
-- Last update: 2015-07-30 -- Last update: 2018-07-03
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- --
-- Top level design of the SVEC-based LIST WR trigger distribution node, with -- Top level design of the SVEC-based LIST WR trigger distribution node, with
-- FMC Fine Delay in slot 2 and FMC TDC in slot 1. -- FMC Fine Delay in slot 2 and FMC TDC in slot 1.
...@@ -18,20 +18,20 @@ ...@@ -18,20 +18,20 @@
-- --
-- Copyright (c) 2014 CERN -- Copyright (c) 2014 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation; -- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any -- either version 2.1 of the License, or (at your option) any
-- later version. -- later version.
-- --
-- This source is distributed in the hope that it will be -- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more -- PURPOSE. See the GNU Lesser General Public License for more
-- details. -- details.
-- --
-- You should have received a copy of the GNU Lesser General -- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it -- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html -- from http://www.gnu.org/licenses/lgpl-2.1.html
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -42,10 +42,10 @@ use ieee.std_logic_1164.all; ...@@ -42,10 +42,10 @@ use ieee.std_logic_1164.all;
library work; library work;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.svec_node_pkg.all; use work.svec_node_pkg.all;
use work.xvme64x_core_pkg.all; use work.vme64x_pkg.all;
use work.fine_delay_pkg.all; use work.fine_delay_pkg.all;
use work.wrn_mqueue_pkg.all; use work.mt_mqueue_pkg.all;
use work.wr_node_pkg.all; use work.mock_turtle_pkg.all;
use work.tdc_core_pkg.all; use work.tdc_core_pkg.all;
library unisim; library unisim;
...@@ -275,48 +275,41 @@ architecture rtl of svec_top is ...@@ -275,48 +275,41 @@ architecture rtl of svec_top is
(0 => x"00000000"); (0 => x"00000000");
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) := constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000"); (0 => x"10000000");
constant c_hmq_config : t_wrn_mqueue_config :=
(
out_slot_count => 4,
out_slot_config => (
0 => (width => 128, entries => 8), -- control CPU 0 (to host)
1 => (width => 128, entries => 8), -- control CPU 1 (to host)
2 => (width => 16, entries => 128), -- log CPU 0
3 => (width => 16, entries => 128), -- log CPU 1
others => (0, 0)),
in_slot_count => 2,
in_slot_config => (
0 => (width => 32, entries => 8), -- control CPU 0 (from host)
1 => (width => 32, entries => 8), -- control CPU 1 (from host)
others => (0, 0)
)
);
constant c_node_config : t_mt_config :=
constant c_rmq_config : t_wrn_mqueue_config :=
(
out_slot_count => 1,
out_slot_config => (
0 => (width => 128, entries => 16), -- TDC remote out
others => (0, 0)),
in_slot_count => 1,
in_slot_config => (
0 => (width => 128, entries => 16), -- FD remote in
others => (0, 0)
)
);
constant c_node_config : t_wr_node_config :=
( (
app_id => x"115790de", app_id => x"115790de",
cpu_count => 2, cpu_count => 2,
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0), cpu_config => (
hmq_config => c_hmq_config, 0 | 1 => (
rmq_config => c_rmq_config, memsize => 32768,
hmq_config => (
slot_count => 2,
slot_config => (
0 => (
-- Control
entries_bits => 3,
width_bits => 7,
header_bits => 2,
endpoint_id => x"0000_0000"),
1 => (
-- Log
entries_bits => 7,
width_bits => 4,
header_bits => 2,
endpoint_id => x"0000_0000"),
others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => (
slot_count => 1,
slot_config => (
0 => (
entries_bits => 4,
width_bits => 7,
header_bits => 4,
endpoint_id => x"0000_0000"),
others => c_DUMMY_MT_MQUEUE_SLOT))),
others => (
0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
shared_mem_size => 8192 shared_mem_size => 8192
); );
...@@ -386,11 +379,11 @@ architecture rtl of svec_top is ...@@ -386,11 +379,11 @@ architecture rtl of svec_top is
signal CONTROL : std_logic_vector(35 downto 0); signal CONTROL : std_logic_vector(35 downto 0);
signal TRIG : std_logic_vector(127 downto 0); signal TRIG : std_logic_vector(127 downto 0);
begin begin
U_Node_Template : svec_node_template U_Node_Template : entity work.svec_node_template
generic map ( generic map (
g_fmc0_sdb => c_tdc_sdb_record, g_fmc0_sdb => c_tdc_sdb_record,
g_fmc0_vic_vector => c_tdc_vector, g_fmc0_vic_vector => c_tdc_vector,
...@@ -399,7 +392,7 @@ begin ...@@ -399,7 +392,7 @@ begin
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_wr_phy => true, g_with_wr_phy => true,
g_double_wrnode_core_clock => false, g_double_wrnode_core_clock => false,
g_with_white_rabbit => true, g_with_white_rabbit => true,
g_wr_node_config => c_node_config) g_wr_node_config => c_node_config)
port map ( port map (
rst_n_a_i => rst_n_a_i, rst_n_a_i => rst_n_a_i,
...@@ -488,7 +481,8 @@ begin ...@@ -488,7 +481,8 @@ begin
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles, tm_cycles_o => tm_cycles,
carrier_scl_b => carrier_scl_b, carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b); carrier_sda_b => carrier_sda_b,
led_state_i => (others => '0'));
U_TDC_Core : fmc_tdc_wrapper U_TDC_Core : fmc_tdc_wrapper
...@@ -741,6 +735,3 @@ begin ...@@ -741,6 +735,3 @@ begin
end rtl; end rtl;
hdl/top/svec/node_template/svec_node_pkg.vhd
View file @ 9652761d
...@@ -6,11 +6,11 @@ ...@@ -6,11 +6,11 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2014-04-01 -- Created : 2014-04-01
-- Last update: 2015-07-23 -- Last update: 2018-06-29
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
-- --
-- Sample top level SVEC wrapper with WR node code and WR PTP core embedded. -- Sample top level SVEC wrapper with WR node code and WR PTP core embedded.
-- Just connect your FMCs and configure the mqueues to start working! -- Just connect your FMCs and configure the mqueues to start working!
...@@ -18,20 +18,20 @@ ...@@ -18,20 +18,20 @@
-- --
-- Copyright (c) 2014-2015 CERN -- Copyright (c) 2014-2015 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation; -- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any -- either version 2.1 of the License, or (at your option) any
-- later version. -- later version.
-- --
-- This source is distributed in the hope that it will be -- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more -- PURPOSE. See the GNU Lesser General Public License for more
-- details. -- details.
-- --
-- You should have received a copy of the GNU Lesser General -- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it -- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html -- from http://www.gnu.org/licenses/lgpl-2.1.html
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -41,19 +41,19 @@ use ieee.STD_LOGIC_1164.all; ...@@ -41,19 +41,19 @@ use ieee.STD_LOGIC_1164.all;
library work; library work;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wr_node_pkg.all; use work.mock_turtle_pkg.all;
use work.wrn_mqueue_pkg.all; use work.mt_mqueue_pkg.all;
use work.xvme64x_core_pkg.all; use work.vme64x_pkg.all;
package svec_node_pkg is package svec_node_pkg is
constant c_unused_wisbone_slave_out : t_wishbone_slave_out := constant c_unused_wisbone_slave_out : t_wishbone_slave_out :=
('1', '0', '0', '0', '0', x"deadbeef"); ('1', '0', '0', '0', x"deadbeef");
constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00010000"); constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00010000");
constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00018000"); constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00018000");
component svec_node_template is component svec_node_template is
generic ( generic (
g_fmc0_sdb : t_sdb_record := c_unused_fmc0_record; g_fmc0_sdb : t_sdb_record := c_unused_fmc0_record;
...@@ -64,7 +64,7 @@ package svec_node_pkg is ...@@ -64,7 +64,7 @@ package svec_node_pkg is
g_simulation : boolean := false; g_simulation : boolean := false;
g_with_wr_phy : boolean := true; g_with_wr_phy : boolean := true;
g_double_wrnode_core_clock : boolean := false; g_double_wrnode_core_clock : boolean := false;
g_wr_node_config : t_wr_node_config; g_wr_node_config : t_mt_config;
g_use_external_fp_leds : boolean := false); g_use_external_fp_leds : boolean := false);
port ( port (
-- power-up reset from the SVEC system FPGA -- power-up reset from the SVEC system FPGA
......
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