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White Rabbit Trigger Distribution
Commit abaa0981 authored by Tristan Gingold's avatar Tristan Gingold
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wrtd builder: can handle fd_tdc.

parent 404aa4cf
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builder/fmc-delay-1ns-8cha/inst.vhd deleted 100644 → 0
View file @ 404aa4cf
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #{n})
-----------------------------------------------------------------------------
cmp_fd_tdc_start{n} : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE)
port map (
O => fmc{n}_fd_tdc_start,
I => fmc{n}_fd_tdc_start_p_i,
IB => fmc{n}_fd_tdc_start_n_i);
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr1_pll_reset,
LOCKED => ddr1_pll_locked,
CLK_IN1_P => fmc{n}_fd_clk_ref_p_i,
CLK_IN1_N => fmc{n}_fd_clk_ref_n_i,
CLK_OUT1 => dcm1_clk_ref_0,
CLK_OUT2 => dcm1_clk_ref_180);
ddr1_pll_reset <= not fmc{n}_fd_pll_status_i;
fmc{n}_fd_pll_status <= fmc{n}_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core{n} : fine_delay_core
generic map (
g_with_wr_core => TRUE,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => dcm1_clk_ref_0,
clk_ref_180_i => dcm1_clk_ref_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr1_pll_locked,
trig_a_i => fmc{n}_fd_trig_a_i,
tdc_cal_pulse_o => fmc{n}_fd_tdc_cal_pulse_o,
tdc_start_i => fmc{n}_fd_tdc_start,
dmtd_fb_in_i => fmc{n}_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc{n}_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc{n}_fd_dmtd_clk_o,
led_trig_o => fmc{n}_fd_led_trig_o,
ext_rst_n_o => fmc{n}_fd_ext_rst_n_o,
pll_status_i => fmc{n}_fd_pll_status,
acam_d_o => fmc{n}_fd_tdc_data_out,
acam_d_i => fmc{n}_fd_tdc_data_in,
acam_d_oen_o => fmc{n}_fd_tdc_data_oe,
acam_emptyf_i => fmc{n}_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc{n}_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc{n}_fd_tdc_wr_n_o,
acam_rd_n_o => fmc{n}_fd_tdc_rd_n_o,
acam_start_dis_o => fmc{n}_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc{n}_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc{n}_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc{n}_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc{n}_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc{n}_fd_spi_sclk_o,
spi_mosi_o => fmc{n}_fd_spi_mosi_o,
spi_miso_i => fmc{n}_fd_spi_miso_i,
delay_len_o => fmc{n}_fd_delay_len_o,
delay_val_o => fmc{n}_fd_delay_val_o,
delay_pulse_o => fmc{n}_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
owr_en_o => fmc{n}_fd_owr_en,
owr_i => fmc{n}_fd_owr_in,
i2c_scl_oen_o => fmc{n}_fd_scl_out,
i2c_scl_i => fmc{n}_fd_scl_in,
i2c_sda_oen_o => fmc{n}_fd_sda_out,
i2c_sda_i => fmc{n}_fd_sda_in,
fmc_present_n_i => fmc{n}_prsntm2c_n_i,
wb_adr_i => fmc{n}_mux_wb_out.adr,
wb_dat_i => fmc{n}_mux_wb_out.dat,
wb_dat_o => fmc{n}_mux_wb_in.dat,
wb_sel_i => fmc{n}_mux_wb_out.sel,
wb_cyc_i => fmc{n}_mux_wb_out.cyc,
wb_stb_i => fmc{n}_mux_wb_out.stb,
wb_we_i => fmc{n}_mux_wb_out.we,
wb_ack_o => fmc{n}_mux_wb_in.ack,
wb_stall_o => fmc{n}_mux_wb_in.stall,
wb_irq_o => fmc_host_irq({n}));
cmp_fmc{n}_wb_mux : xwb_crossbar
generic map (
g_num_masters => 2,
g_num_slaves => 1,
g_registered => TRUE,
g_address => c_FMC_MUX_ADDR,
g_mask => c_FMC_MUX_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out(1),
slave_i(1) => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o(0) => fmc_dp_wb_in(1),
slave_o(1) => cnx_slave_out(c_WB_SLAVE_FMC{n}),
master_i(0) => fmc{n}_mux_wb_in,
master_o(0) => fmc{n}_mux_wb_out);
fmc{n}_mux_wb_in.err <= '0';
fmc{n}_mux_wb_in.rty <= '0';
-- tristate buffer for the TDC data bus:
fmc{n}_fd_tdc_d_b <= fmc{n}_fd_tdc_data_out when fmc{n}_fd_tdc_data_oe = '1' else (others => 'Z');
fmc{n}_fd_tdc_oe_n_o <= '1';
fmc{n}_fd_tdc_data_in <= fmc{n}_fd_tdc_d_b;
fmc{n}_fd_onewire_b <= '0' when fmc{n}_fd_owr_en = '1' else 'Z';
fmc{n}_fd_owr_in <= fmc{n}_fd_onewire_b;
fmc{n}_scl_b <= '0' when (fmc{n}_fd_scl_out = '0') else 'Z';
fmc{n}_sda_b <= '0' when (fmc{n}_fd_sda_out = '0') else 'Z';
fmc{n}_fd_scl_in <= fmc{n}_scl_b;
fmc{n}_fd_sda_in <= fmc{n}_sda_b;
builder/fmc-delay-1ns-8cha/svec-fmc0.ucf 0 → 100644
View file @ abaa0981
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
NET "fmc0_fd_clk_ref_p_i" LOC = "E16";
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_clk_ref_n_i" LOC = "D16";
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_p_i" LOC = "H15";
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_n_i" LOC = "G15";
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_delay_len_o[3]" LOC = "G10";
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = "F10";
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = "E9";
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = "F9";
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = "F12";
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[1]" LOC = "E11";
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[2]" LOC = "G12";
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[0]" LOC = "F11";
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" LOC = "J12";
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = "H11";
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = "L11";
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = "J13";
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = "L12";
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_spi_mosi_o" LOC = "M13";
NET "fmc0_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_sclk_o" LOC = "L14";
NET "fmc0_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_oe_n_o" LOC = "M15";
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_start_dis_o" LOC = "F13";
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = "F15";
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_cal_pulse_o" LOC = "G14";
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_clk_o" LOC = "J14";
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_wr_n_o" LOC = "B15";
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_alutrigger_o" LOC = "F19";
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_led_trig_o" LOC = "H16";
NET "fmc0_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[26]" LOC = "F17";
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[24]" LOC = "G18";
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[20]" LOC = "F21";
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[22]" LOC = "G20";
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[18]" LOC = "L21";
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[16]" LOC = "M20";
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[10]" LOC = "F23";
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[14]" LOC = "G22";
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[8]" LOC = "B25";
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[12]" LOC = "M19";
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[3]" LOC = "D24";
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[5]" LOC = "E25";
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[7]" LOC = "J22";
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[2]" LOC = "H21";
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_trig_a_i" LOC = "C16";
NET "fmc0_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" LOC = "H12";
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[0]" LOC = "G11";
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = "K11";
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = "H13";
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = "K12";
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_spi_miso_i" LOC = "L13";
NET "fmc0_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_pll_n_o" LOC = "K14";
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_dac_n_o" LOC = "K15";
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_stop_dis_o" LOC = "E13";
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_ext_rst_n_o" LOC = "E15";
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_pll_status_i" LOC = "F14";
NET "fmc0_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_out_i" LOC = "H14";
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_rd_n_o" LOC = "A15";
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_emptyf_i" LOC = "E19";
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_onewire_b" LOC = "G16";
NET "fmc0_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[27]" LOC = "E17";
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[25]" LOC = "F18";
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[21]" LOC = "E21";
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[23]" LOC = "F20";
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[19]" LOC = "K21";
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[17]" LOC = "L20";
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[11]" LOC = "E23";
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[15]" LOC = "F22";
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[9]" LOC = "A25";
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[13]" LOC = "L19";
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[1]" LOC = "C24";
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[4]" LOC = "D25";
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[6]" LOC = "H22";
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[0]" LOC = "G21";
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_in_i" LOC = "A16";
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
builder/fmc-delay-1ns-8cha/svec-fmc1.ucf
View file @ abaa0981
......@@ -181,3 +181,12 @@ NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
builder/fmc-delay-1ns-8cha/top.vhd
View file @ abaa0981
[use]
use work.fine_delay_pkg.all;
[ports]
---------------------------------------------------------------------------
-- FMC slot {n} pins (FDELAY mezzanine)
---------------------------------------------------------------------------
......@@ -37,3 +40,153 @@
fmc{n}_fd_ext_rst_n_o : out std_logic;
fmc{n}_fd_onewire_b : inout std_logic;
[sdb-decl]
[sdb-layout]
c_WB_SLAVE_FMC{n} => f_sdb_embed_device(c_FD_SDB_DEVICE, x"{addr}"),
[decls]
-- Muxed Host and MT WB interface to FMC{n}
signal fmc{n}_mux_wb_out : t_wishbone_master_out;
signal fmc{n}_mux_wb_in : t_wishbone_master_in;
-- Misc FMC signals
signal fmc{n}_fd_tdc_start : std_logic;
signal ddr{n}_pll_reset : std_logic;
signal ddr{n}_pll_locked : std_logic;
signal fmc{n}_fd_pll_status : std_logic;
signal fmc{n}_fd_tdc_data_out : std_logic_vector(27 downto 0);
signal fmc{n}_fd_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc{n}_fd_tdc_data_oe : std_logic;
signal fmc{n}_fd_owr_en, fmc{n}_fd_owr_in : std_logic;
signal fmc{n}_fd_scl_in : std_logic;
signal fmc{n}_fd_sda_in : std_logic;
signal fmc{n}_clk_125m_180 : std_logic;
[body]
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #{n})
-----------------------------------------------------------------------------
cmp_fd_tdc_start{n} : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE)
port map (
O => fmc{n}_fd_tdc_start,
I => fmc{n}_fd_tdc_start_p_i,
IB => fmc{n}_fd_tdc_start_n_i);
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr{n}_pll_reset,
LOCKED => ddr{n}_pll_locked,
CLK_IN1_P => fmc{n}_fd_clk_ref_p_i,
CLK_IN1_N => fmc{n}_fd_clk_ref_n_i,
CLK_OUT1 => fmc{n}_clk_125m,
CLK_OUT2 => fmc{n}_clk_125m_180);
ddr{n}_pll_reset <= not fmc{n}_fd_pll_status_i;
fmc{n}_fd_pll_status <= fmc{n}_fd_pll_status_i and ddr{n}_pll_locked;
U_FineDelay_Core{n} : fine_delay_core
generic map (
g_with_wr_core => TRUE,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => fmc{n}_clk_125m,
clk_ref_180_i => fmc{n}_clk_125m_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr{n}_pll_locked,
trig_a_i => fmc{n}_fd_trig_a_i,
tdc_cal_pulse_o => fmc{n}_fd_tdc_cal_pulse_o,
tdc_start_i => fmc{n}_fd_tdc_start,
dmtd_fb_in_i => fmc{n}_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc{n}_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc{n}_fd_dmtd_clk_o,
led_trig_o => fmc{n}_fd_led_trig_o,
ext_rst_n_o => fmc{n}_fd_ext_rst_n_o,
pll_status_i => fmc{n}_fd_pll_status,
acam_d_o => fmc{n}_fd_tdc_data_out,
acam_d_i => fmc{n}_fd_tdc_data_in,
acam_d_oen_o => fmc{n}_fd_tdc_data_oe,
acam_emptyf_i => fmc{n}_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc{n}_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc{n}_fd_tdc_wr_n_o,
acam_rd_n_o => fmc{n}_fd_tdc_rd_n_o,
acam_start_dis_o => fmc{n}_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc{n}_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc{n}_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc{n}_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc{n}_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc{n}_fd_spi_sclk_o,
spi_mosi_o => fmc{n}_fd_spi_mosi_o,
spi_miso_i => fmc{n}_fd_spi_miso_i,
delay_len_o => fmc{n}_fd_delay_len_o,
delay_val_o => fmc{n}_fd_delay_val_o,
delay_pulse_o => fmc{n}_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
owr_en_o => fmc{n}_fd_owr_en,
owr_i => fmc{n}_fd_owr_in,
i2c_scl_oen_o => fmc{n}_scl_out,
i2c_scl_i => fmc{n}_fd_scl_in,
i2c_sda_oen_o => fmc{n}_sda_out,
i2c_sda_i => fmc{n}_fd_sda_in,
fmc_present_n_i => fmc{n}_prsntm2c_n_i,
wb_adr_i => fmc{n}_mux_wb_out.adr,
wb_dat_i => fmc{n}_mux_wb_out.dat,
wb_dat_o => fmc{n}_mux_wb_in.dat,
wb_sel_i => fmc{n}_mux_wb_out.sel,
wb_cyc_i => fmc{n}_mux_wb_out.cyc,
wb_stb_i => fmc{n}_mux_wb_out.stb,
wb_we_i => fmc{n}_mux_wb_out.we,
wb_ack_o => fmc{n}_mux_wb_in.ack,
wb_stall_o => fmc{n}_mux_wb_in.stall,
wb_irq_o => fmc_host_irq({n}));
cmp_fmc{n}_wb_mux : xwb_crossbar
generic map (
g_num_masters => 2,
g_num_slaves => 1,
g_registered => TRUE,
g_address => c_FMC_MUX_ADDR,
g_mask => c_FMC_MUX_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out({n}),
slave_i(1) => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o(0) => fmc_dp_wb_in({n}),
slave_o(1) => cnx_slave_out(c_WB_SLAVE_FMC{n}),
master_i(0) => fmc{n}_mux_wb_in,
master_o(0) => fmc{n}_mux_wb_out);
fmc{n}_mux_wb_in.err <= '0';
fmc{n}_mux_wb_in.rty <= '0';
-- tristate buffer for the TDC data bus:
fmc{n}_fd_tdc_d_b <= fmc{n}_fd_tdc_data_out when fmc{n}_fd_tdc_data_oe = '1' else (others => 'Z');
fmc{n}_fd_tdc_oe_n_o <= '1';
fmc{n}_fd_tdc_data_in <= fmc{n}_fd_tdc_d_b;
fmc{n}_fd_onewire_b <= '0' when fmc{n}_fd_owr_en = '1' else 'Z';
fmc{n}_fd_owr_in <= fmc{n}_fd_onewire_b;
fmc{n}_fd_scl_in <= fmc{n}_scl_b;
fmc{n}_fd_sda_in <= fmc{n}_sda_b;
builder/fmc-tdc-1ns-5cha/inst.vhd deleted 100644 → 0
View file @ 404aa4cf
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #{n})
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
generic map (
g_simulation => f_int2bool(g_simulation),
g_with_direct_readout => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
pll_sclk_o => fmc{n}_tdc_pll_sclk_o,
pll_sdi_o => fmc{n}_tdc_pll_sdi_o,
pll_cs_o => fmc{n}_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc{n}_tdc_pll_dac_sync_n_o,
pll_sdo_i => fmc{n}_tdc_pll_sdo_i,
pll_status_i => fmc{n}_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc{n}_tdc_125m_clk_p_i,
tdc_clk_125m_n_i => fmc{n}_tdc_125m_clk_n_i,
acam_refclk_p_i => fmc{n}_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc{n}_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc{n}_tdc_start_from_fpga_o,
err_flag_i => fmc{n}_tdc_err_flag_i,
int_flag_i => fmc{n}_tdc_int_flag_i,
start_dis_o => fmc{n}_tdc_start_dis_o,
stop_dis_o => fmc{n}_tdc_stop_dis_o,
data_bus_io => fmc{n}_tdc_data_bus_io,
address_o => fmc{n}_tdc_address_o,
cs_n_o => fmc{n}_tdc_cs_n_o,
oe_n_o => fmc{n}_tdc_oe_n_o,
rd_n_o => fmc{n}_tdc_rd_n_o,
wr_n_o => fmc{n}_tdc_wr_n_o,
ef1_i => fmc{n}_tdc_ef1_i,
ef2_i => fmc{n}_tdc_ef2_i,
enable_inputs_o => fmc{n}_tdc_enable_inputs_o,
term_en_1_o => fmc{n}_tdc_term_en_1_o,
term_en_2_o => fmc{n}_tdc_term_en_2_o,
term_en_3_o => fmc{n}_tdc_term_en_3_o,
term_en_4_o => fmc{n}_tdc_term_en_4_o,
term_en_5_o => fmc{n}_tdc_term_en_5_o,
tdc_led_status_o => fmc{n}_tdc_led_status_o,
tdc_led_trig1_o => fmc{n}_tdc_led_trig1_o,
tdc_led_trig2_o => fmc{n}_tdc_led_trig2_o,
tdc_led_trig3_o => fmc{n}_tdc_led_trig3_o,
tdc_led_trig4_o => fmc{n}_tdc_led_trig4_o,
tdc_led_trig5_o => fmc{n}_tdc_led_trig5_o,
tdc_in_fpga_1_i => fmc{n}_tdc_in_fpga_1_i,
tdc_in_fpga_2_i => fmc{n}_tdc_in_fpga_2_i,
tdc_in_fpga_3_i => fmc{n}_tdc_in_fpga_3_i,
tdc_in_fpga_4_i => fmc{n}_tdc_in_fpga_4_i,
tdc_in_fpga_5_i => fmc{n}_tdc_in_fpga_5_i,
mezz_scl_i => fmc{n}_scl_b,
mezz_sda_i => fmc{n}_sda_b,
mezz_scl_o => fmc{n}_scl_out,
mezz_sda_o => fmc{n}_sda_out,
mezz_one_wire_b => fmc{n}_tdc_one_wire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(0),
direct_slave_i => fmc_dp_wb_out(0),
direct_slave_o => fmc_dp_wb_in(0),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC{n}),
irq_o => fmc_host_irq({n}),
clk_125m_tdc_o => tdc_clk_125m);
fmc{n}_scl_b <= '0' when fmc{n}_scl_out = '0' else 'Z';
fmc{n}_sda_b <= '0' when fmc{n}_sda_out = '0' else 'Z';
builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf
View file @ abaa0981
......@@ -137,5 +137,14 @@ NET "fmc0_tdc_wr_n_o" SLEW = SLOW;
NET "fmc0_tdc_wr_n_o" DRIVE = 4;
NET "fmc0_tdc_enable_inputs_o" LOC = "J12";
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_one_wire_b" LOC = "H12";
NET "fmc0_tdc_one_wire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_onewire_b" LOC = "H12";
NET "fmc0_tdc_onewire_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# input clocks
NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf 0 → 100644
View file @ abaa0981
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "fmc1_tdc_acam_refclk_p_i" LOC = AF16;
NET "fmc1_tdc_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_acam_refclk_n_i" LOC = AG16;
NET "fmc1_tdc_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_125m_clk_p_i" LOC = AH16;
NET "fmc1_tdc_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_125m_clk_n_i" LOC = AK16;
NET "fmc1_tdc_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_led_trig1_o" LOC = Y20;
NET "fmc1_tdc_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig2_o" LOC = W19;
NET "fmc1_tdc_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig3_o" LOC = Y19;
NET "fmc1_tdc_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_1_o" LOC = AJ17;
NET "fmc1_tdc_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_2_o" LOC = AK17;
NET "fmc1_tdc_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef1_i" LOC = AB14;
NET "fmc1_tdc_ef1_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef2_i" LOC = AC14;
NET "fmc1_tdc_ef2_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_3_o" LOC = AE19;
NET "fmc1_tdc_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_4_o" LOC = AF19;
NET "fmc1_tdc_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_5_o" LOC = AE24;
NET "fmc1_tdc_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_status_o" LOC = AF24;
NET "fmc1_tdc_led_status_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig4_o" LOC = Y21;
NET "fmc1_tdc_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig5_o" LOC = AA21;
NET "fmc1_tdc_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sclk_o" LOC = AF25;
NET "fmc1_tdc_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_dac_sync_n_o" LOC = AG25;
NET "fmc1_tdc_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_cs_n_o" LOC = AC19;
NET "fmc1_tdc_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_cs_n_o" LOC = AD19;
NET "fmc1_tdc_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_err_flag_i" LOC = Y17;
NET "fmc1_tdc_err_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_int_flag_i" LOC = AA17;
NET "fmc1_tdc_int_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_dis_o" LOC = AB17;
NET "fmc1_tdc_start_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_stop_dis_o" LOC = AD17;
NET "fmc1_tdc_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdo_i" LOC = AC20;
NET "fmc1_tdc_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_status_i" LOC = AD24;
NET "fmc1_tdc_pll_status_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdi_o" LOC = AB20;
NET "fmc1_tdc_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_from_fpga_o" LOC = AC24;
NET "fmc1_tdc_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[27]" LOC = AA15;
NET "fmc1_tdc_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[26]" LOC = Y15;
NET "fmc1_tdc_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[25]" LOC = AD15;
NET "fmc1_tdc_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[24]" LOC = AC15;
NET "fmc1_tdc_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[23]" LOC = AB16;
NET "fmc1_tdc_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[22]" LOC = Y16;
NET "fmc1_tdc_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[21]" LOC = AF15;
NET "fmc1_tdc_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[20]" LOC = AE15;
NET "fmc1_tdc_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[19]" LOC = AA14;
NET "fmc1_tdc_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[18]" LOC = Y14;
NET "fmc1_tdc_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[17]" LOC = Y13;
NET "fmc1_tdc_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[16]" LOC = W14;
NET "fmc1_tdc_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[15]" LOC = AE12;
NET "fmc1_tdc_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[14]" LOC = AD12;
NET "fmc1_tdc_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[13]" LOC = AF11;
NET "fmc1_tdc_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[12]" LOC = AE11;
NET "fmc1_tdc_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[11]" LOC = AC12;
NET "fmc1_tdc_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[10]" LOC = AB12;
NET "fmc1_tdc_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[9]" LOC = AE10;
NET "fmc1_tdc_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[8]" LOC = AD10;
NET "fmc1_tdc_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[7]" LOC = AH8;
NET "fmc1_tdc_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[6]" LOC = AK15;
NET "fmc1_tdc_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[5]" LOC = AG8;
NET "fmc1_tdc_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[4]" LOC = AJ15;
NET "fmc1_tdc_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[3]" LOC = AF13;
NET "fmc1_tdc_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[2]" LOC = AE13;
NET "fmc1_tdc_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[1]" LOC = AD11;
NET "fmc1_tdc_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[0]" LOC = AC11;
NET "fmc1_tdc_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[3]" LOC = AF23;
NET "fmc1_tdc_address_o[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[2]" LOC = AE23;
NET "fmc1_tdc_address_o[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[1]" LOC = AF21;
NET "fmc1_tdc_address_o[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[0]" LOC = AE21;
NET "fmc1_tdc_address_o[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_oe_n_o" LOC = AD22;
NET "fmc1_tdc_oe_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_rd_n_o" LOC = AD16;
NET "fmc1_tdc_rd_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_wr_n_o" LOC = AC16;
NET "fmc1_tdc_wr_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_enable_inputs_o" LOC = AA19;
NET "fmc1_tdc_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_onewire_b" LOC = AB19;
NET "fmc1_tdc_onewire_b" IOSTANDARD = LVCMOS25;
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# input clocks
NET "fmc1_tdc_125m_clk_n_i" TNM_NET = fmc1_tdc_125m_clk_n_i;
TIMESPEC TS_fmc1_tdc_125m_clk_n_i = PERIOD "fmc1_tdc_125m_clk_n_i" 8 ns HIGH 50%;
builder/fmc-tdc-1ns-5cha/top.vhd
View file @ abaa0981
[use]
use work.tdc_core_pkg.all;
[ports]
---------------------------------------------------------------------------
-- FMC slot {n} pins (TDC mezzanine)
---------------------------------------------------------------------------
......@@ -40,7 +43,7 @@
fmc{n}_tdc_term_en_5_o : out std_logic;
-- TDC1 1-wire UniqueID & Thermometer
fmc{n}_tdc_one_wire_b : inout std_logic;
fmc{n}_tdc_onewire_b : inout std_logic;
-- TDC1 EEPROM I2C
fmc{n}_tdc_scl_b : inout std_logic;
......@@ -61,3 +64,82 @@
fmc{n}_tdc_in_fpga_3_i : in std_logic;
fmc{n}_tdc_in_fpga_4_i : in std_logic;
fmc{n}_tdc_in_fpga_5_i : in std_logic;
[sdb-decl]
constant c_tdc{n}_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000");
[sdb-layout]
c_WB_SLAVE_FMC{n} => f_sdb_embed_bridge(c_tdc{n}_bridge_sdb, x"{addr}"),
[body]
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #{n})
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
generic map (
g_simulation => f_int2bool(g_simulation),
g_with_direct_readout => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
pll_sclk_o => fmc{n}_tdc_pll_sclk_o,
pll_sdi_o => fmc{n}_tdc_pll_sdi_o,
pll_cs_o => fmc{n}_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc{n}_tdc_pll_dac_sync_n_o,
pll_sdo_i => fmc{n}_tdc_pll_sdo_i,
pll_status_i => fmc{n}_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc{n}_tdc_125m_clk_p_i,
tdc_clk_125m_n_i => fmc{n}_tdc_125m_clk_n_i,
acam_refclk_p_i => fmc{n}_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc{n}_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc{n}_tdc_start_from_fpga_o,
err_flag_i => fmc{n}_tdc_err_flag_i,
int_flag_i => fmc{n}_tdc_int_flag_i,
start_dis_o => fmc{n}_tdc_start_dis_o,
stop_dis_o => fmc{n}_tdc_stop_dis_o,
data_bus_io => fmc{n}_tdc_data_bus_io,
address_o => fmc{n}_tdc_address_o,
cs_n_o => fmc{n}_tdc_cs_n_o,
oe_n_o => fmc{n}_tdc_oe_n_o,
rd_n_o => fmc{n}_tdc_rd_n_o,
wr_n_o => fmc{n}_tdc_wr_n_o,
ef1_i => fmc{n}_tdc_ef1_i,
ef2_i => fmc{n}_tdc_ef2_i,
enable_inputs_o => fmc{n}_tdc_enable_inputs_o,
term_en_1_o => fmc{n}_tdc_term_en_1_o,
term_en_2_o => fmc{n}_tdc_term_en_2_o,
term_en_3_o => fmc{n}_tdc_term_en_3_o,
term_en_4_o => fmc{n}_tdc_term_en_4_o,
term_en_5_o => fmc{n}_tdc_term_en_5_o,
tdc_led_status_o => fmc{n}_tdc_led_status_o,
tdc_led_trig1_o => fmc{n}_tdc_led_trig1_o,
tdc_led_trig2_o => fmc{n}_tdc_led_trig2_o,
tdc_led_trig3_o => fmc{n}_tdc_led_trig3_o,
tdc_led_trig4_o => fmc{n}_tdc_led_trig4_o,
tdc_led_trig5_o => fmc{n}_tdc_led_trig5_o,
tdc_in_fpga_1_i => fmc{n}_tdc_in_fpga_1_i,
tdc_in_fpga_2_i => fmc{n}_tdc_in_fpga_2_i,
tdc_in_fpga_3_i => fmc{n}_tdc_in_fpga_3_i,
tdc_in_fpga_4_i => fmc{n}_tdc_in_fpga_4_i,
tdc_in_fpga_5_i => fmc{n}_tdc_in_fpga_5_i,
mezz_scl_i => fmc{n}_scl_b,
mezz_sda_i => fmc{n}_sda_b,
mezz_scl_o => fmc{n}_scl_out,
mezz_sda_o => fmc{n}_sda_out,
mezz_one_wire_b => fmc{n}_tdc_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
direct_slave_i => fmc_dp_wb_out({n}),
direct_slave_o => fmc_dp_wb_in({n}),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC{n}),
irq_o => fmc_host_irq({n}),
clk_125m_tdc_o => fmc{n}_clk_125m);
builder/svec/top.ucf
View file @ abaa0981
......@@ -378,12 +378,6 @@ TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
......@@ -392,8 +386,8 @@ TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
......@@ -402,14 +396,14 @@ TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys";
TIMEGRP "fdl_sync"="synchronizers" EXCEPT "dcm1_clk_ref_0";
TIMEGRP "tdc_sync"="synchronizers" EXCEPT "tdc_clk_125m";
TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
TIMEGRP "phy_sync"="synchronizers" EXCEPT "phy_rx_rbclk";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "fdl_sync" 20ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "tdc_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
# Relax the path where TAI time crosses from WR ref to MT sys clock
......
builder/svec/top.vhd
View file @ abaa0981
......@@ -38,16 +38,15 @@ use work.wr_svec_pkg.all;
use work.wr_fabric_pkg.all;
use work.mt_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.tdc_core_pkg.all;
use work.fine_delay_pkg.all;
use work.synthesis_descriptor.all;
{use}
library unisim;
use unisim.vcomponents.all;
entity {name}_top is
generic (
g_WR_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_WR_DPRAM_INITF : string := "{topdir}/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../../software/firmware/fd/wrtd-rt-fd.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
......@@ -206,7 +205,7 @@ architecture arch of {name}_top is
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 5;
constant c_NUM_WB_SLAVES : integer := {nslots} + 3;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_VME : integer := 0;
......@@ -215,10 +214,10 @@ architecture arch of {name}_top is
constant c_WB_SLAVE_VIC : integer := 0;
constant c_WB_SLAVE_FMC0 : integer := 1;
constant c_WB_SLAVE_FMC1 : integer := 2;
constant c_WB_SLAVE_MT : integer := 3;
constant c_WB_SLAVE_WRC : integer := 4;
constant c_WB_DESC_SYN : integer := 5;
constant c_WB_DESC_URL : integer := 6;
constant c_WB_SLAVE_MT : integer := {nslots} + 1;
constant c_WB_SLAVE_WRC : integer := {nslots} + 2;
constant c_WB_DESC_SYN : integer := {nslots} + 3;
constant c_WB_DESC_URL : integer := {nslots} + 4;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -228,14 +227,12 @@ architecture arch of {name}_top is
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_tdc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000");
{sdb-decl}
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_WB_SLAVE_FMC0 => f_sdb_embed_bridge(c_tdc_bridge_sdb, x"00010000"),
c_WB_SLAVE_FMC1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00018000"),
{sdb-layout}
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
......@@ -276,15 +273,14 @@ architecture arch of {name}_top is
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_ref : std_logic;
signal tdc_clk_125m : std_logic;
signal dcm1_clk_ref_0 : std_logic;
signal dcm1_clk_ref_180 : std_logic;
signal fmc0_clk_125m : std_logic;
signal fmc1_clk_125m : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of tdc_clk_125m : signal is "TRUE";
attribute keep of dcm1_clk_ref_0 : signal is "TRUE";
attribute keep of fmc0_clk_125m : signal is "TRUE";
attribute keep of fmc1_clk_125m : signal is "TRUE";
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
......@@ -348,8 +344,8 @@ architecture arch of {name}_top is
signal eth_rx_in : t_wrf_sink_in;
-- MT Dedicated WB interfaces to FMCs
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1);
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1);
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to {ncpus} - 1);
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to {ncpus} - 1);
-- WRPC TM interface and aux clocks
signal tm_link_up : std_logic;
......@@ -364,30 +360,17 @@ architecture arch of {name}_top is
-- MT TM interface
signal tm : t_mt_timing_if;
-- Muxed Host and MT WB interface to FMC1
signal fmc1_mux_wb_out : t_wishbone_master_out;
signal fmc1_mux_wb_in : t_wishbone_master_in;
signal fmc0_scl_out : std_logic := '1';
signal fmc0_sda_out : std_logic := '1';
-- Misc FMC signals
signal fmc1_fd_tdc_start : std_logic;
signal ddr1_pll_reset : std_logic;
signal ddr1_pll_locked : std_logic;
signal fmc1_fd_pll_status : std_logic;
signal fmc1_fd_tdc_data_out : std_logic_vector(27 downto 0);
signal fmc1_fd_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc1_fd_tdc_data_oe : std_logic;
signal fmc1_fd_owr_en, fmc1_fd_owr_in : std_logic;
signal fmc1_fd_scl_out, fmc1_fd_scl_in : std_logic;
signal fmc1_fd_sda_out, fmc1_fd_sda_in : std_logic;
signal fmc0_scl_out : std_logic;
signal fmc0_sda_out : std_logic;
signal fmc1_scl_out : std_logic := '1';
signal fmc1_sda_out : std_logic := '1';
attribute iob : string;
attribute iob of pps : signal is "FORCE";
{decls}
begin -- architecture arch
-----------------------------------------------------------------------------
......@@ -603,8 +586,8 @@ begin -- architecture arch
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
clk_aux_i(0) => tdc_clk_125m,
clk_aux_i(1) => dcm1_clk_ref_0,
clk_aux_i(0) => fmc0_clk_125m,
clk_aux_i(1) => fmc1_clk_125m,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
......@@ -676,7 +659,15 @@ begin -- architecture arch
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
{instances}
-- fmc i2c
fmc0_scl_b <= '0' when (fmc0_scl_out = '0') else 'Z';
fmc0_sda_b <= '0' when (fmc0_sda_out = '0') else 'Z';
fmc1_scl_b <= '0' when (fmc1_scl_out = '0') else 'Z';
fmc1_sda_b <= '0' when (fmc1_sda_out = '0') else 'Z';
{body}
-----------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
......
builder/wrtd_builder.py
View file @ abaa0981
......@@ -4,6 +4,7 @@ import sys
import os.path
import glob
import shutil
import re
data_dir = None
......@@ -14,7 +15,6 @@ def error(msg):
class Result(object):
def __init__(self):
self.top_template = None
self.mt_config = None
......@@ -25,23 +25,22 @@ def parse(filename):
return d['wrtd-board']
def build_mt_config(desc):
def build_mt_config(desc, res):
appid = desc['appid']
cpus = desc['cpus']
ncpus = len([ x for x in cpus if isinstance(x, int) ])
res = """
cfg = """
constant c_mt_config : t_mt_config :=
(
app_id => x"{:08x}",
cpu_count => {},
cpu_config => (""".format(
appid, ncpus)
appid, res.ncpus)
# Be sure that cpus are defined from 0 to N-1.
for i in range(ncpus):
for i in range(res.ncpus):
cpu = desc['cpus'].get(i, None)
if cpu == None:
error('No definition for cpu {}'.format(i))
res += """
cfg += """
{} => (
memsize => {},
hmq_config => (""".format(
......@@ -49,7 +48,7 @@ def build_mt_config(desc):
hmq = cpu.get('hmq', None)
if hmq is not None:
res += """
cfg += """
slot_count => 1,
slot_config => (
0 => (
......@@ -59,13 +58,13 @@ def build_mt_config(desc):
endpoint_id => x"0000_0000",
enable_config_space => FALSE),""".format(
hmq['log_entries'])
res += """
cfg += """
others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => ("""
rmq = cpu.get('rmq', None)
if rmq is not None:
res += """
cfg += """
slot_count => 1,
slot_config => (
0 => (
......@@ -75,24 +74,17 @@ def build_mt_config(desc):
endpoint_id => x"0000_0000",
enable_config_space => TRUE),""".format(
rmq['log_entries'])
res += """
cfg += """
others => c_DUMMY_MT_MQUEUE_SLOT))),"""
res += """
cfg += """
others => (
0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
shared_mem_size => {}
);""".format(cpus['shared_memsize'] * 1024 // 4)
return res
res.mt_config = cfg
def board_svec(res, desc, slots):
if len(slots) > 2:
error('SVEC can have only 2 slots')
for k in slots.keys():
if k not in [0, 1]:
error('incorrect slot id {} for SVEC'.format(k))
boards = { 'svec': board_svec }
board_slots = { 'svec': [0, 1]}
def maybe_mkdir(path):
......@@ -110,21 +102,20 @@ def compute_fetchto(relfile):
def generate_hdl(res, board, slots):
# Build ports
ports = ""
# Read template
templates = { 'use': "", 'ports': "", 'decls': "", 'body': "",
'sdb-decl': "", 'sdb-layout': ""}
section_re = re.compile(r"\[(.+)\]$")
section = None
for k, v in slots.items():
addr = "{:08x}".format(0x10000 + k * 0x8000)
tmpl = open(os.path.join(data_dir, v, 'top.vhd')).read()
ports += tmpl.format(n=k)
ports += '\n'
res.ports = ports
# Build instances
insts = ""
for k, v in slots.items():
tmpl = open(os.path.join(data_dir, v, 'inst.vhd')).read()
insts += tmpl.format(n=k)
insts += '\n'
res.instances = insts
for l in tmpl.splitlines():
m = section_re.match(l)
if m:
section = m.group(1)
else:
templates[section] += l.format(n=k, addr=addr) + '\n'
# Top vhdl file
maybe_mkdir("hdl")
......@@ -132,14 +123,17 @@ def generate_hdl(res, board, slots):
maybe_mkdir(os.path.join("hdl", "top", res.name))
top_filename = os.path.join("hdl", "top", res.name,
"{}_top.vhd".format(res.name))
topdir = compute_fetchto(top_filename)
print("Writing {}".format(top_filename))
top_template = open(os.path.join(data_dir, board, 'top.vhd')).read()
top = open(top_filename, "w")
top.write(top_template.format(name=res.name,
ports=res.ports,
mt_config=res.mt_config,
instances=res.instances))
ncpus=res.ncpus,
topdir=topdir,
nslots=len(slots),
**templates))
top.close()
# Top Manifest
......@@ -204,14 +198,18 @@ def main():
desc = parse(args.filename)
res.name = desc['name']
res.mt_config = build_mt_config(desc)
slots = desc['slots']
res.ncpus = len([ x for x in desc['cpus'] if isinstance(x, int) ])
build_mt_config(desc, res)
desc_slots = desc['slots']
board = desc['board']
if board not in boards:
slots = board_slots.get(board, None)
if slots is None:
error('unknown board "{}"'.format(board))
boards[board](res, desc, slots)
for k, v in desc_slots.items():
if k not in slots:
error('unknown slot "{}"'.format(k))
generate_hdl(res, board, slots)
generate_hdl(res, board, desc_slots)
if __name__ == '__main__':
main()
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