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White Rabbit Trigger Distribution
Commit bb32cd08 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: improvements to reach timing closure in SPEC150T FMC-ADC reference design. Tested, works

parent 79a7656f
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Showing with 10 additions and 2 deletions
general-cores @ caad0595
Subproject commit 0ed0cf1d2d8b21a9d92fea949a1ccaa03d9883a2 Subproject commit caad0595a00d6f69aa59993a790c1aa3c8fd691f
gn4124-core @ c9d96ee0
Subproject commit ceb3c1227613e17d265573501fe0539b8314fb13 Subproject commit c9d96ee08abce9440ec79e5d2c11359876ddb486
hdl/syn/wrtd_ref_spec150t_adc/syn_extra_steps.tcl
View file @ bb32cd08
...@@ -14,13 +14,19 @@ xilinx::project open $project_file ...@@ -14,13 +14,19 @@ xilinx::project open $project_file
# Not respected by ISE when passed through hdlmake: # Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs # 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map # 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map" xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route" xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes" xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes" xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On" xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ bb32cd08
...@@ -214,6 +214,8 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25"; ...@@ -214,6 +214,8 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t" IOB = FALSE; INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t" IOB = FALSE;
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE; INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE;
NET "fmc?_adc_gpio*" IOB = FALSE;
#=============================================================================== #===============================================================================
# Timing constraints and exceptions # Timing constraints and exceptions
#=============================================================================== #===============================================================================
......
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