Add MCS build, update README.md

e2fa8940 · Tom Levens · 8b0e7842 · e2fa8940 · e2fa8940 · e2fa8940
Commit e2fa8940 authored May 01, 2019 by Tom Levens
6 changed files
--- a/README.md
+++ b/README.md
@@ -9,31 +9,70 @@ OHWR hardware components:
 The gateware implements the BST decoder and extracts the following signals on
 the front-panel LEMO outputs:

-  * **LEMO 1:** bunch clock (40 MHz, 50% duty cycle)
-  * **LEMO 2:** turn clock (43 kHz, 25 ns pulse)
+  * **LEMO 1:** bunch clock         (40 MHz, 50% duty cycle)
+  * **LEMO 2:** turn clock          (43 kHz, 25 ns pulse)
  * **LEMO 3:** injection pre-pulse (23 us pulse)
-  * **LEMO 4:** turn clock divided by N (23 us pulse)
+  * **LEMO 4:** UA9 trigger         (23 us pulse)

-## Building the firmware
+## Hardware configuration

-Building the firmware requires [hdlmake](https://www.ohwr.org/project/hdl-make/)
-to create the project.
+The TTC_FMC should be installed in FMC slot 1 (bottom) on the SVEC.

-Generally the following steps are required to be executed from the root
-directory of the project repository to build a firmware:
+## Building the gateware
+
+### Required tooling
+
+Building the gateware requires Xilinx ISE 14.7 running on Linux.
+
+[hdlmake] is required in order to create the ISE project.
+
+Generating the MCS file for flashing the PROM requires the *gensdbfs* utility
+from the [fpga-config-space] repository. Clone the repository and execute:

 ```sh
-cd hdl/syn/
-./update_sdb.sh
-hdlmake
+cd fpga-config-space/sdbfs/lib
+make
+cd ../userspace
 make
 ```

-After this, you should end up with a *svec_top.bit* file which can be loaded
-onto a SVEC via VME with the following command:
+Then copy the *gensdbfs* binary to somewhere in your PATH.
+
+[hdlmake]: https://www.ohwr.org/project/hdl-make
+[fpga-config-space]: https://ohwr.org/project/fpga-config-space
+
+### Synthesising the gateware
+
+Generally the following steps are required to be executed from the */hdl/syn/*
+directory to synthesise the gateware image:
+
+```sh
+./update_sdb.sh # Generate the file ../rtl/sdb_meta_pkg.sh
+hdlmake         # Generate the ISE project
+make            # Run ISE to perform the synthesis
+```
+
+After ISE has completed, you should end up with the file *svec_top.bit*.
+
+### Loading the gateware
+
+The gateware can be loaded onto a SVEC over VME by running the following
+command on the front-end:

 ```sh
 sudo dd if=svec_top.bit of=/dev/svec.0 obs=10M
 ```

-(assuming the SVEC driver is installed with LUN=0)
+This is assuming the SVEC driver is installed with LUN=0. If not, then adjust
+the device number as appropriate.
+
+### Flashing the PROM
+
+To generate the MCS file for flashing the PROM, run the script:
+
+```sh
+./build_mcs.sh
+```
+
+The resulting *image.mcs* file can be flashed via JTAG to the M25P128 SPI PROM
+attached to the XC6SLX9 system FPGA.
--- a/hdl/syn/.gitignore
+++ b/hdl/syn/.gitignore
@@ -2,3 +2,6 @@
 !.gitignore
 !Manifest.py
 !update_sdb.sh
+!build_mcs.sh
+!fs/
+!fs/*
--- a/hdl/syn/build_mcs.sh
+++ b/hdl/syn/build_mcs.sh
+#!/bin/bash
+
+# A trivial script to build the SDB flash image for the SVEC. Requires sdb-tools installed in the system
+
+PROMGEN=`which promgen`
+GENSDBFS=`which gensdbfs`
+
+if [ ! -f "$PROMGEN" ]; then
+	echo "You seem to not have the promgen utility. Do you have Xilinx ISE installed?"
+	exit
+fi
+
+if [ ! -f "$GENSDBFS" ]; then
+	echo "You seem to not have the gensdbfs. Have you compiled and installed it (check the manual)?"
+	exit
+fi
+
+
+gensdbfs fs image.bin
+promgen -p mcs -o image.mcs -spi -data_file up 0 image.bin  -w
+#./bin2vmf image.bin > image.vmf
--- a/hdl/syn/fs/--SDB-CONFIG--
+++ b/hdl/syn/fs/--SDB-CONFIG--
+
+# This is an example config file, that can be used to build a filesystem
+# from this very directory. Please note that gensdbfs doesn't look for
+# config files in subdirectories but only in the tol-level one.
+
+.
+	vendor = 0xce42
+	device = 0x5fec
+	position = 0x600000
+
+svec-bootloader.bin
+	position = 0
+
+afpga.bin
+	position = 0x100000
--- a/hdl/syn/fs/afpga.bin
+++ b/hdl/syn/fs/afpga.bin
+../svec_top.bit
\ No newline at end of file
--- a/hdl/syn/fs/svec-bootloader.bin
+++ b/hdl/syn/fs/svec-bootloader.bin