Gateware for CONV-TTL-BLO boards
Project description
Gateware implemented in VHDL for the Xilinx Spartan-6 FPGA ensures most of the functionalities for the CONV-TTL-BLO board:
- Pulse regeneration based on input trigger for each of the six input channels
- Dynamic control of repetition frequency based on a thermal model of PCB blocking output stage overheating
- Communication via I2C and ELMA
protocol
- Retrieve board status, gateware and hardware version
- Remote reprogramming
- Diagnostics
- Converter board ID
- Gateware/hardware version
- On-board switches and RTM lines status (RTM detection)
- Input line state
- Input pulse counters, separate counters for TTL and BLO inputs.
- Time-tagging of last 128 input pulses
- Per-channel latest pulse timestamp readout
- Remote reset
- Manual pulse triggering
- System errors
- 1-wirte thermometer readout and unique chip ID available in memory-mapped registers.
- Controlling pulse and system status LEDs
Releases
- Latest release released
- Releases page
Documentation
- CONV-TTL-BLO HDL Guide
- Converter boards common gateware
- Gateware user guide
- ELMA I2C protocol
- Gateware test procedure
Status
** Date ** | ** Event ** |
---|---|
31-07-2013 | Separate gateware project created |
07-01-2014 | Golden gateware released |
07-01-2014 | Gateware v1.0 released |
10-03-2014 | Gateware v2.0 released |
09-04-2014 | Gateware v2.1 released |
15-04-2014 | Gateware v2.2 released |
25-04-2014 | Golden gateware v0.1 released |
26-09-2014 | Gateware v3.0 released |
29-09-2014 | Golden gateware v0.2 released |
27-01-2017 | Review held for new release |
10-03-2017 | Gateware v4.0 released |
Theodor-Adrian Stana, Erik van der Bij, Denia Bouhired June 19th, 2017