|
|
# Blocking output stage
|
|
|
|
|
|
This can be caused by incorrect gateware loaded on the FPGA, which may
|
|
|
cause longer, or even continuous, pulses on the MOSFET gate. Higher
|
|
|
pulse repetition rates may also cause this problem.
|
|
|
|
|
|
# LT Spice Simulation of the Blocking output stage
|
|
|
|
|
|
Below, in fig.1, is the circuit simulated in LTSpice. Of course specific
|
... | ... | |