ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the…

ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the latter includes the former.

ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the…
ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the latter includes the former.
405ce250 · Dimitris Lampridis · 33b31655 · 405ce250
Commit 405ce250 authored Dec 13, 2018 by Dimitris Lampridis
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ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +3 -3

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--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -8,7 +8,7 @@
 --              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-07-13
-- Last update: 2018-11-12
+-- Last update: 2018-12-13
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Wishbone interface for DDR3 controller.
@@ -224,7 +224,7 @@ begin
        ddr_wr_data <= (others => '0');
        ddr_wr_en   <= '0';
      else
-        if (wb_stb_valid = '1') and (wb_cyc_i = '1') and (wb_we_i = '1') then
+        if (wb_stb_valid = '1') and (wb_we_i = '1') then
          ddr_wr_en <= '1';
        else
          ddr_wr_en <= '0';
@@ -290,7 +290,7 @@ begin
      else
        if (wb_cyc_f_edge = '1') then
          ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
-        elsif (wb_stb_valid = '1' and wb_cyc_i = '1') then
+        elsif (wb_stb_valid = '1') then
          if (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
            ddr_burst_cnt <= to_unsigned(1, ddr_burst_cnt'length);
          else