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f95568c4
Commit
f95568c4
authored
Jan 16, 2020
by
A. Hahn
Browse files
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Plain Diff
eb_usb_core: removed wishbone int signals
parent
35bca79a
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Showing
2 changed files
with
65 additions
and
68 deletions
+65
-68
ez_usb.vhd
hdl/eb_usb_core/ez_usb.vhd
+23
-25
ez_usb_fifos.vhd
hdl/eb_usb_core/ez_usb_fifos.vhd
+42
-43
No files found.
hdl/eb_usb_core/ez_usb.vhd
View file @
f95568c4
...
...
@@ -43,7 +43,7 @@ entity ez_usb is
-- Wishbone interface
master_i
:
in
t_wishbone_master_in
;
master_o
:
out
t_wishbone_master_out
;
-- USB Console
uart_o
:
out
std_logic
;
uart_i
:
in
std_logic
;
...
...
@@ -67,7 +67,7 @@ entity ez_usb is
end
ez_usb
;
architecture
rtl
of
ez_usb
is
component
uart_baud_gen
generic
(
g_baud_acc_width
:
integer
);
...
...
@@ -104,7 +104,7 @@ architecture rtl of ez_usb is
signal
rx_ready
:
std_logic
;
signal
baud_tick
:
std_logic
;
signal
baud8_tick
:
std_logic
;
signal
uart2usb_uart_i
:
t_wishbone_slave_in
;
signal
uart2usb_uart_o
:
t_wishbone_slave_out
;
signal
uart2usb_usb_i
:
t_wishbone_slave_in
;
...
...
@@ -113,7 +113,7 @@ architecture rtl of ez_usb is
signal
usb2uart_usb_o
:
t_wishbone_slave_out
;
signal
usb2uart_uart_i
:
t_wishbone_slave_in
;
signal
usb2uart_uart_o
:
t_wishbone_slave_out
;
signal
eb2usb_m
:
t_wishbone_slave_in
;
signal
eb2usb_s
:
t_wishbone_slave_out
;
signal
usb2eb_usb_i
:
t_wishbone_slave_in
;
...
...
@@ -121,18 +121,18 @@ architecture rtl of ez_usb is
signal
usb2eb_eb_i
:
t_wishbone_slave_in
;
signal
usb2eb_eb_i2
:
t_wishbone_slave_in
;
signal
usb2eb_eb_o
:
t_wishbone_slave_out
;
signal
ebcyc
:
std_logic_vector
(
2
downto
0
);
signal
shift
:
std_logic_vector
(
3
downto
0
);
signal
speed
:
std_logic_vector
(
2
downto
0
);
signal
baudrate
:
std_logic_vector
(
16
downto
0
)
:
=
"00000001111000110"
;
constant
c_ticks
:
natural
:
=
5
*
g_sys_freq
;
-- 5ms
constant
c_tick_bits
:
natural
:
=
f_ceil_log2
(
c_ticks
);
signal
nreset
:
std_logic
:
=
'0'
;
signal
counter
:
unsigned
(
c_tick_bits
-1
downto
0
)
:
=
to_unsigned
(
c_ticks
-1
,
c_tick_bits
);
begin
rstn_o
<=
nreset
;
...
...
@@ -163,13 +163,13 @@ begin
ebcyc
<=
ebcyc_i
&
ebcyc
(
ebcyc
'left
downto
1
);
shift
<=
shift_i
&
shift
(
shift
'left
downto
1
);
speed
<=
speed_i
&
speed
(
speed
'left
downto
1
);
if
shift
(
1
)
=
'1'
and
shift
(
0
)
=
'0'
then
baudrate
<=
speed
(
0
)
&
baudrate
(
baudrate
'left
downto
1
);
end
if
;
end
if
;
end
process
;
EZUSB
:
ez_usb_fifos
generic
map
(
g_clock_period
=>
g_clock_period
,
...
...
@@ -180,17 +180,17 @@ begin
port
map
(
clk_sys_i
=>
clk_sys_i
,
rstn_i
=>
nreset
,
slave_i
(
0
)
=>
usb2eb_usb_i
,
-- EP2 (out) = host writes to EB
slave_i
(
1
)
=>
usb2uart_usb_i
,
-- EP4 (out) = host writes to uart
slave_i
(
2
)
=>
eb2usb_m
,
-- EP6 (in) = EB writes to host
slave_i
(
3
)
=>
uart2usb_usb_i
,
-- EP8 (in) = uart writes to host
slave_o
(
0
)
=>
usb2eb_usb_o
,
slave_o
(
1
)
=>
usb2uart_usb_o
,
slave_o
(
2
)
=>
eb2usb_s
,
slave_o
(
3
)
=>
uart2usb_usb_o
,
fifoadr_o
=>
fifoadr_o
,
readyn_i
=>
readyn_i
,
fulln_i
=>
fulln_i
,
...
...
@@ -202,7 +202,7 @@ begin
fd_i
=>
fd_i
,
fd_o
=>
fd_o
,
fd_oen_o
=>
fd_oen_o
);
-- Both USB and UART are slaves
UART2USB
:
xwb_streamer
generic
map
(
...
...
@@ -214,7 +214,7 @@ begin
r_master_i
=>
uart2usb_uart_o
,
w_master_o
=>
uart2usb_usb_i
,
w_master_i
=>
uart2usb_usb_o
);
USB2UART
:
xwb_streamer
generic
map
(
logRingLen
=>
8
)
-- allow up to 256 bytes in buffer
...
...
@@ -225,7 +225,7 @@ begin
r_master_i
=>
usb2uart_usb_o
,
w_master_o
=>
usb2uart_uart_i
,
w_master_i
=>
usb2uart_uart_o
);
U_BAUD_GEN
:
uart_baud_gen
generic
map
(
g_baud_acc_width
=>
16
)
...
...
@@ -235,7 +235,7 @@ begin
baudrate_i
=>
baudrate
,
baud_tick_o
=>
baud_tick
,
baud8_tick_o
=>
baud8_tick
);
-- all bytes sent to the device will be delivered reliably
-- ... but, of course, the WR LM32 driver drops bytes like mad
U_TX
:
uart_async_tx
-- USB2UART
...
...
@@ -251,8 +251,7 @@ begin
usb2uart_uart_o
.
err
<=
'0'
;
usb2uart_uart_o
.
rty
<=
'0'
;
usb2uart_uart_o
.
dat
<=
(
others
=>
'0'
);
usb2uart_uart_o
.
int
<=
'0'
;
-- this will drop bytes once buffers are full (no host connected)
U_RX
:
uart_async_rx
-- UART2USB
port
map
(
...
...
@@ -266,10 +265,9 @@ begin
uart2usb_uart_o
.
ack
<=
rx_ready
and
uart2usb_uart_i
.
cyc
and
uart2usb_uart_i
.
stb
;
uart2usb_uart_o
.
err
<=
'0'
;
uart2usb_uart_o
.
rty
<=
'0'
;
uart2usb_uart_o
.
int
<=
'0'
;
uart2usb_uart_o
.
dat
(
31
downto
8
)
<=
(
others
=>
'0'
);
uart2usb_uart_o
.
stall
<=
not
rx_ready
;
-- Both EB input and USB output are slaves
USB2EB
:
xwb_streamer
generic
map
(
...
...
@@ -281,15 +279,15 @@ begin
r_master_i
=>
usb2eb_usb_o
,
w_master_o
=>
usb2eb_eb_i
,
w_master_i
=>
usb2eb_eb_o
);
usb2eb_eb_i2
.
cyc
<=
ebcyc
(
0
);
usb2eb_eb_i2
.
stb
<=
usb2eb_eb_i
.
stb
and
usb2eb_eb_i
.
cyc
;
usb2eb_eb_i2
.
adr
<=
usb2eb_eb_i
.
adr
;
usb2eb_eb_i2
.
sel
<=
usb2eb_eb_i
.
sel
;
usb2eb_eb_i2
.
we
<=
usb2eb_eb_i
.
we
;
usb2eb_eb_i2
.
dat
<=
usb2eb_eb_i
.
dat
;
EB
:
eb_raw_slave
generic
map
(
g_sdb_address
=>
x"00000000"
&
g_sdb_address
,
...
...
@@ -305,5 +303,5 @@ begin
cfg_slave_i
=>
cc_dummy_slave_in
,
master_o
=>
master_o
,
master_i
=>
master_i
);
end
rtl
;
hdl/eb_usb_core/ez_usb_fifos.vhd
View file @
f95568c4
...
...
@@ -76,12 +76,12 @@ architecture rtl of ez_usb_fifos is
constant
c_tFDH
:
integer
:
=
10
;
-- FIFO DATA to SLWR hold time
constant
c_tPEpwl
:
integer
:
=
50
;
-- PKTEND pulse width low
constant
c_tPEpwh
:
integer
:
=
50
;
-- PKTEND pulse width high
type
t_state
is
(
LATCH_FLAGS
,
DISPATCH
,
SET_ADDR
,
DRIVE_READ
,
LATCH_DATA
,
IDLE_READ
,
DRIVE_WRITE
,
IDLE_WRITE
,
IDLE_DATA
,
DRIVE_PKTEND
,
IDLE_PKTEND
);
function
f_cycles
(
x
:
integer
)
return
integer
is
begin
if
x
+
g_margin
<=
0
then
return
1
;
else
return
(
x
+
g_margin
+
g_clock_period
-1
)
/
g_clock_period
;
end
if
;
...
...
@@ -90,12 +90,12 @@ architecture rtl of ez_usb_fifos is
begin
return
x
*
g_clock_period
;
end
f_ns
;
function
f_max
(
x
,
y
:
integer
)
return
integer
is
begin
if
x
>
y
then
return
x
;
else
return
y
;
end
if
;
end
f_max
;
-- Derive the number of cycles we stay in each state
constant
c_latch_flags
:
integer
:
=
2
;
-- >= 2 to synchronize async signal
constant
c_dispatch
:
integer
:
=
1
;
...
...
@@ -119,16 +119,16 @@ architecture rtl of ez_usb_fifos is
f_max
(
c_tXFLG_e
+
g_board_delay
*
2
-
f_ns
(
c_drive_pktend
),
c_tFAH
-
f_ns
(
c_latch_flags
+
c_dispatch
))));
constant
c_max_count
:
integer
:
=
f_max
(
c_latch_flags
,
f_max
(
c_dispatch
,
f_max
(
c_set_addr
,
f_max
(
c_drive_read
,
f_max
(
c_latch_data
,
f_max
(
c_idle_read
,
f_max
(
c_drive_write
,
f_max
(
c_idle_write
,
constant
c_max_count
:
integer
:
=
f_max
(
c_latch_flags
,
f_max
(
c_dispatch
,
f_max
(
c_set_addr
,
f_max
(
c_drive_read
,
f_max
(
c_latch_data
,
f_max
(
c_idle_read
,
f_max
(
c_drive_write
,
f_max
(
c_idle_write
,
f_max
(
c_idle_data
,
f_max
(
c_drive_pktend
,
c_idle_pktend
))))))))));
subtype
word
is
std_logic_vector
(
g_fifo_width
-1
downto
0
);
type
words
is
array
(
natural
range
<>
)
of
word
;
signal
state
:
t_state
:
=
LATCH_FLAGS
;
signal
notready
:
std_logic_vector
(
c_latch_flags
-1
downto
0
)
:
=
(
others
=>
'1'
);
signal
notempty
:
std_logic_vector
(
c_latch_flags
-1
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -143,7 +143,7 @@ architecture rtl of ez_usb_fifos is
signal
write
:
std_logic_vector
(
g_num_fifos
-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
stall
:
std_logic_vector
(
g_num_fifos
-1
downto
0
)
:
=
(
others
=>
'1'
);
signal
ack
:
std_logic_vector
(
g_num_fifos
-1
downto
0
)
:
=
(
others
=>
'0'
);
begin
-- Drive unregistered WB signals
...
...
@@ -151,14 +151,13 @@ begin
slave_o
(
i
)
.
ack
<=
ack
(
i
);
slave_o
(
i
)
.
err
<=
'0'
;
slave_o
(
i
)
.
rty
<=
'0'
;
slave_o
(
i
)
.
int
<=
'0'
;
slave_o
(
i
)
.
stall
<=
stall
(
i
);
slave_o
(
i
)
.
dat
(
word
'range
)
<=
dat4wb
(
i
);
slave_o
(
i
)
.
dat
(
c_wishbone_data_width
-1
downto
g_fifo_width
)
<=
(
others
=>
'0'
);
end
generate
;
fifoadr_o
<=
std_logic_vector
(
addr
);
sync
:
process
(
clk_sys_i
)
is
begin
if
rising_edge
(
clk_sys_i
)
then
...
...
@@ -167,7 +166,7 @@ begin
notempty
<=
emptyn_i
&
notempty
(
notempty
'left
downto
1
);
end
if
;
end
process
;
fsm
:
process
(
clk_sys_i
,
rstn_i
)
is
begin
if
rstn_i
=
'0'
then
...
...
@@ -182,23 +181,23 @@ begin
write
<=
(
others
=>
'0'
);
stall
<=
(
others
=>
'1'
);
ack
<=
(
others
=>
'0'
);
sloen_o
<=
'1'
;
slrdn_o
<=
'1'
;
slwrn_o
<=
'1'
;
pktendn_o
<=
'1'
;
fd_o
<=
(
others
=>
'0'
);
fd_oen_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
case
state
is
when
LATCH_FLAGS
=>
ack
(
to_integer
(
addr
))
<=
'0'
;
stall
(
to_integer
(
addr
))
<=
request
(
to_integer
(
addr
));
if
stall
(
to_integer
(
addr
))
=
'0'
and
slave_i
(
to_integer
(
addr
))
.
cyc
=
'1'
and
slave_i
(
to_integer
(
addr
))
.
stb
=
'1'
then
...
...
@@ -207,7 +206,7 @@ begin
write
(
to_integer
(
addr
))
<=
slave_i
(
to_integer
(
addr
))
.
we
;
dat4usb
(
to_integer
(
addr
))
<=
slave_i
(
to_integer
(
addr
))
.
dat
(
word
'range
);
end
if
;
if
count
/=
c_latch_flags
-1
then
count
<=
count
+
1
;
else
...
...
@@ -215,11 +214,11 @@ begin
state
<=
DISPATCH
;
count
<=
(
others
=>
'0'
);
end
if
;
when
DISPATCH
=>
state
<=
SET_ADDR
;
-- default
count
<=
(
others
=>
'0'
);
if
request
(
to_integer
(
addr
))
=
'1'
then
if
write
(
to_integer
(
addr
))
=
'1'
then
if
notfull
(
0
)
=
'1'
and
notready
(
0
)
=
'0'
then
...
...
@@ -237,7 +236,7 @@ begin
state
<=
DRIVE_PKTEND
;
end
if
;
end
if
;
when
SET_ADDR
=>
if
count
=
0
then
if
addr
=
g_num_fifos
-1
then
...
...
@@ -246,43 +245,43 @@ begin
addr
<=
addr
+
1
;
end
if
;
end
if
;
if
count
/=
c_set_addr
-1
then
count
<=
count
+
1
;
else
state
<=
LATCH_FLAGS
;
count
<=
(
others
=>
'0'
);
end
if
;
when
DRIVE_READ
=>
sloen_o
<=
'0'
;
slrdn_o
<=
'0'
;
if
count
/=
c_drive_read
-1
then
count
<=
count
+
1
;
else
state
<=
LATCH_DATA
;
count
<=
(
others
=>
'0'
);
end
if
;
when
LATCH_DATA
=>
sloen_o
<=
'1'
;
if
count
=
0
then
fd_r
<=
fd_i
;
end
if
;
if
count
/=
c_latch_data
-1
then
count
<=
count
+
1
;
else
state
<=
IDLE_READ
;
count
<=
(
others
=>
'0'
);
end
if
;
when
IDLE_READ
=>
dat4wb
(
to_integer
(
addr
))
<=
fd_r
;
slrdn_o
<=
'1'
;
if
count
/=
c_idle_read
-1
then
count
<=
count
+
1
;
else
...
...
@@ -290,33 +289,33 @@ begin
count
<=
(
others
=>
'0'
);
ack
(
to_integer
(
addr
))
<=
'1'
;
end
if
;
when
DRIVE_WRITE
=>
slwrn_o
<=
'0'
;
fd_oen_o
<=
'1'
;
fd_o
<=
dat4usb
(
to_integer
(
addr
));
needend
(
to_integer
(
addr
))
<=
'1'
;
if
count
/=
c_drive_write
-1
then
count
<=
count
+
1
;
else
state
<=
IDLE_WRITE
;
count
<=
(
others
=>
'0'
);
end
if
;
when
IDLE_WRITE
=>
slwrn_o
<=
'1'
;
if
count
/=
c_idle_write
-1
then
count
<=
count
+
1
;
else
state
<=
IDLE_DATA
;
count
<=
(
others
=>
'0'
);
end
if
;
when
IDLE_DATA
=>
fd_oen_o
<=
'0'
;
if
count
/=
c_idle_data
-1
then
count
<=
count
+
1
;
else
...
...
@@ -324,21 +323,21 @@ begin
count
<=
(
others
=>
'0'
);
ack
(
to_integer
(
addr
))
<=
'1'
;
end
if
;
when
DRIVE_PKTEND
=>
pktendn_o
<=
'0'
;
needend
(
to_integer
(
addr
))
<=
'0'
;
if
count
/=
c_drive_pktend
-1
then
count
<=
count
+
1
;
else
state
<=
IDLE_PKTEND
;
count
<=
(
others
=>
'0'
);
end
if
;
when
IDLE_PKTEND
=>
pktendn_o
<=
'1'
;
if
count
/=
c_idle_pktend
-1
then
count
<=
count
+
1
;
else
...
...
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