Open
Milestone
Schematic done
When the schematic is done and reviewed and we can start layout.
Unstarted Issues (open and unassigned)
25
- Bug in negative LDO enable generation
- Wrong net label in FMC_Bus
- OSC1 frequency stability/tuning range
- Optimize clock distribution
- WR DAC reference voltage
- Trigger comparator hysteresis
- Issues with "No ERC" markers
- FMC I2C bus addressing
- Output clock coupling
- IC4O, IC43 - what's the role of this chip in the design?
- Cleanup remaining warnings
- Use Net Classes / Parameter Sets for specifying things likes controlled impedance
- Use "Differential Pair" directive and suffixes for differential signal pairs
- IC52 missing decoupling cap in VREF pin
- Non-existent 3P3VAUX voltage at monitoring ADC input
- FMC I2C bus pull-ups
- Remove unused signals from the FMCCLOCKS harness
- VREF_A_M2C connection can be removed
- Consider adding placement comments for T1/T2
- Fix TVS rating labels in ClockTrigIO
- Consider renaming the CH[1,2]CAL[50R,1M]P signals
- Move input signal connectors higher in schematic hierarchy
- Top-level schematic is difficult to read
- Attenuator AC doesn't match simulation file and hard to read
- Is Vadj = 2.2V realistic?
Ongoing Issues (open and assigned)
1
Completed Issues (closed)
1