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Tom Levens authored
The SVEC base design has constraints for gc_sync_register but this is never instantiated in this design. Therefore ISE gives an error during synthesis. To avoid this error I have added an extra "dummy" gc_sync_register for synchronising the FP GPIO inputs. This can be removed once this issue is resolved: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25
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