Commits · 28563a921a4414e53bfec3b858f35f1bf117926a · Projects / FMC DEL 1ns 4cha

24 Nov, 2023 2 commits
- Merge branch '31-release-v-3-1-0' into 'master' · 28563a92
  Dimitris Lampridis authored Nov 24, 2023
```
Resolve "release v.3.1.0"

Closes #31

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!22
```
  28563a92
- update changelog · 36abf5a2
  Dimitris Lampridis authored Nov 22, 2023
  
  36abf5a2
22 Nov, 2023 14 commits
- Merge branch '19-automate-convention-version-assignment' into 'master' · f86a2896
  Dimitris Lampridis authored Nov 22, 2023
```
Resolve "automate convention version assignment"

Closes #19

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!21
```
  f86a2896
- hdl: use automatic versioning · bc64573a
  Dimitris Lampridis authored Nov 22, 2023
  
  bc64573a
- hdl: upgrade deps to latest releases · 71c290ec
  Dimitris Lampridis authored Nov 22, 2023
  
  71c290ec
- Merge branch 'pytest-improvements' into 'master' · c2337ed4
  Federico Vaga authored Nov 22, 2023
```
improve pytest

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!18
```
  c2337ed4
- ci: check python style · a11ec120
  Federico Vaga authored Nov 22, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  a11ec120
- tst: add faster test for longer thatn fifo acq · 4c8be336
  Federico Vaga authored Nov 22, 2023
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The internal fifo can store only up to 15 timestamps. We noticed that
with bad configurations that around 100 timestamps it is starting to
missing some. To avoid waiting for 65k samples before detecting the
error, we make a first try with 100.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  4c8be336
- tst: no need to flush twice · 5ddee72c
  Federico Vaga authored Nov 15, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  5ddee72c
- tst: remove unused argument · 8cd532a4
  Federico Vaga authored Nov 15, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  8cd532a4
- tst: repalce fd-id with dev-id · aebc184e
  Federico Vaga authored Nov 10, 2023
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to make it uniform with other projects
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  aebc184e
- tst: flush TDC buffer after use · 8dd82318
  Federico Vaga authored Nov 10, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  8dd82318
- tst: fix slot option default value · 2263aafd
  Federico Vaga authored Nov 10, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  2263aafd
- tst: remove unused fixture · e32057b3
  Federico Vaga authored Nov 10, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  e32057b3
- tst: rename function to convert slot to id · a8e6d1ed
  Federico Vaga authored Nov 10, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  a8e6d1ed
- tst: take more samples for the period test · d609ea3d
  Federico Vaga authored Nov 09, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  d609ea3d
09 Nov, 2023 9 commits

tst: add python requirement file · 6fc96031
Federico Vaga authored Nov 09, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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6fc96031
tst: allow multiple slot tests · 68ca023b
Federico Vaga authored Nov 09, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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68ca023b

tst: improve test_output_counter · 857520ef

Federico Vaga authored Nov 09, 2023

This patch merges two different tests into one to speed up the entire
testing process. Then it improves the merged code.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

857520ef

tst: speed-up flush test · 083259ec
Federico Vaga authored Nov 09, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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083259ec
tst: do not double check sequence numbers · c2529f5d
Federico Vaga authored Nov 08, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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c2529f5d
tst: more test_output_period withing decent time limits · bf0d77f5
Federico Vaga authored Nov 08, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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bf0d77f5

tst: focus more on the second fractions · e66d5c79

Federico Vaga authored Nov 08, 2023

Waiting for potentially 1 minute for each test leads to a very long
verification time with little just 10 tests done. I re-parametrized the
test_output_input_start test to do more with fraction and focus less on
seconds
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

e66d5c79

tst: move to project root directory · 0264df2f
Federico Vaga authored Nov 08, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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0264df2f
tst: allow users to set the slot number · 417558f4
Federico Vaga authored Nov 08, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
417558f4

07 Nov, 2023 6 commits

Merge branch '23-report-error-when-fpga-is-not-configured' into 'master' · 78bc0498

Federico Vaga authored Nov 07, 2023

Resolve "Report error when FPGA is not configured"

Closes #23

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!15

78bc0498

Grammar fix in comment · cfc135b5
Dimitris Lampridis authored Nov 07, 2023

cfc135b5
tools: always use fdelay_strerror to print err strings · 2a478a2d
Federico Vaga authored Nov 06, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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2a478a2d
lib: fix library to be consistent with doc on error · ede2d0c5
Federico Vaga authored Nov 06, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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ede2d0c5
lib: report alarms on configuration · d1165f23
Federico Vaga authored Oct 18, 2023
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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d1165f23

drv: wait for timing config to be applied · 1938dde0

Federico Vaga authored Oct 18, 2023

The update is not immediate, we need to monitor UPD_DONE to be reassured
that values are applied and we can continue.

If this does not happen, then it is a serious hardware problem. That's
why I chose to use WARN_ON.

By returning and error code, we will get a ZIO_ALARM_LOST_TRIGGER, that
userspace needs to check.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

1938dde0

27 Oct, 2023 3 commits
- Merge branch '28-improve-dcr_enable-timing' into 'master' · 2e42bef3
  Dimitris Lampridis authored Oct 27, 2023
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Resolve "Improve dcr_enable timing"

Closes #28

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!16
```
  2e42bef3
- ci: reuse common hdl synthesis job template · f354a5d6
  Dimitris Lampridis authored Oct 27, 2023
  
  f354a5d6
- hdl: register dcr_enable bit to help with timing (#28 ) · 982968c2
  Dimitris Lampridis authored Oct 27, 2023
  
  982968c2
17 Oct, 2023 2 commits
- Merge branch '27-statically-link-library-to-tools' into 'master' · ab8edc42
  Federico Vaga authored Oct 17, 2023
```
Resolve "Statically link library to tools"

Closes #27

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!14
```
  ab8edc42
- software: tools: Makefile: Statically link library to tools · c1d2c339
  Vaibhav Gupta authored Oct 17, 2023
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Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
```
  c1d2c339
03 Oct, 2023 2 commits
- Merge branch '25-build-entire-sw-in-ci' into 'master' · 5ca24281
  Federico Vaga authored Oct 03, 2023
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Resolve "Build entire sw in CI"

Closes #25

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!13
```
  5ca24281
- Add missing License · baf763a1
  Vaibhav Gupta authored Oct 03, 2023
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Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
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  baf763a1
02 Oct, 2023 2 commits
- CI/CD: Use fec-os-sw-build image to build entire software · 38f04164
  Vaibhav Gupta authored Oct 02, 2023
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Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
```
  38f04164
- Update permissions for 'install' and re-structure the mechanism · 9b3c2a2a
  Vaibhav Gupta authored Oct 02, 2023
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Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>
```
  9b3c2a2a