- 22 Nov, 2023 12 commits
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Dimitris Lampridis authored -
Federico Vaga authored
improve pytest See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!18
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Federico Vaga authored
Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The internal fifo can store only up to 15 timestamps. We noticed that with bad configurations that around 100 timestamps it is starting to missing some. To avoid waiting for 65k samples before detecting the error, we make a first try with 100. Signed-off-by: -
Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
to make it uniform with other projects Signed-off-by: -
Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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- 09 Nov, 2023 9 commits
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
This patch merges two different tests into one to speed up the entire testing process. Then it improves the merged code. Signed-off-by: -
Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
Waiting for potentially 1 minute for each test leads to a very long verification time with little just 10 tests done. I re-parametrized the test_output_input_start test to do more with fraction and focus less on seconds Signed-off-by: -
Federico Vaga authored
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Federico Vaga authored
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- 07 Nov, 2023 6 commits
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Federico Vaga authored
Resolve "Report error when FPGA is not configured" Closes #23 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!15
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Dimitris Lampridis authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
The update is not immediate, we need to monitor UPD_DONE to be reassured that values are applied and we can continue. If this does not happen, then it is a serious hardware problem. That's why I chose to use WARN_ON. By returning and error code, we will get a ZIO_ALARM_LOST_TRIGGER, that userspace needs to check. Signed-off-by:
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- 27 Oct, 2023 3 commits
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Dimitris Lampridis authored
Resolve "Improve dcr_enable timing" Closes #28 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!16
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 17 Oct, 2023 2 commits
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Federico Vaga authored
Resolve "Statically link library to tools" Closes #27 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!14
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Vaibhav Gupta authored
Signed-off-by:Vaibhav Gupta <vaibhav.gupta@cern.ch>
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- 03 Oct, 2023 2 commits
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Federico Vaga authored
Resolve "Build entire sw in CI" Closes #25 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!13
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Vaibhav Gupta authored
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- 02 Oct, 2023 2 commits
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Vaibhav Gupta authored
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Vaibhav Gupta authored
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- 01 Aug, 2023 1 commit
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Federico Vaga authored
Resolve "Use project evergreen's template for driver building validation" Closes #24 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!12
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- 20 Jul, 2023 1 commit
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Vaibhav Gupta authored
With project evergreen's CI/CD templates and includes, it is much easier to build CI/Cd of other projects with simple .gitlab-ci.yml file. Signed-off-by:
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- 13 Feb, 2023 2 commits
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Federico Vaga authored
Resolve "Implement hardware monitoring API" Closes #20 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!11
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Vaibhav Gupta authored
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