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Commit af702851 authored by Andrea Boccardi's avatar Andrea Boccardi
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debug leds and FP lemo changes

parent 936d57a5
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Showing with 2296726 additions and 10459 deletions
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.bld
View file @ af702851
Release 12.3 ngdbuild M.70d (nt) Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p
ApplicationFpga.ngc ApplicationFpga.ngd xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
Reading NGO file Reading NGO file
"C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc" ... "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc" ...
...@@ -18,6 +18,7 @@ Done... ...@@ -18,6 +18,7 @@ Done...
Checking expanded design ... Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'FpGpIo_iob4<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
...@@ -37,12 +38,12 @@ Partition Implementation Status ...@@ -37,12 +38,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary: NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 11 Number of warnings: 12
Total memory usage is 83940 kilobytes Total memory usage is 146700 kilobytes
Writing NGD file "ApplicationFpga.ngd" ... Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 3 sec Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "ApplicationFpga.bld"... Writing NGDBUILD log file "ApplicationFpga.bld"...
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.cmd_log
View file @ af702851
...@@ -6,3 +6,27 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -6,3 +6,27 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.gise
View file @ af702851
...@@ -107,7 +107,7 @@ ...@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292838673" xil_pn:in_ck="4072638633301905625" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1292838659"> <transform xil_pn:end_ts="1292855052" xil_pn:in_ck="4072638633301905625" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1292855045">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839133" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1292839127"> <transform xil_pn:end_ts="1292855056" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1292855052">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -139,9 +139,11 @@ ...@@ -139,9 +139,11 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839186" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292839133"> <transform xil_pn:end_ts="1292855079" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292855056">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ApplicationFpga.pcf"/> <outfile xil_pn:name="ApplicationFpga.pcf"/>
<outfile xil_pn:name="ApplicationFpga_map.map"/> <outfile xil_pn:name="ApplicationFpga_map.map"/>
<outfile xil_pn:name="ApplicationFpga_map.mrp"/> <outfile xil_pn:name="ApplicationFpga_map.mrp"/>
...@@ -152,7 +154,7 @@ ...@@ -152,7 +154,7 @@
<outfile xil_pn:name="ApplicationFpga_usage.xml"/> <outfile xil_pn:name="ApplicationFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839259" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292839186"> <transform xil_pn:end_ts="1292855116" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292855079">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -167,7 +169,7 @@ ...@@ -167,7 +169,7 @@
<outfile xil_pn:name="ApplicationFpga_par.xrpt"/> <outfile xil_pn:name="ApplicationFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839392" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292839336"> <transform xil_pn:end_ts="1292855146" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292855116">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -183,7 +185,12 @@ ...@@ -183,7 +185,12 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839259" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292839237"> <transform xil_pn:end_ts="1292855153" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292855146">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="applicationfpga.isc"/>
</transform>
<transform xil_pn:end_ts="1292855116" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292855105">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ApplicationFpga.twr"/> <outfile xil_pn:name="ApplicationFpga.twr"/>
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ncd
View file @ af702851
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trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc
View file @ af702851
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngd
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngr
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.pad
View file @ af702851
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010 Mon Dec 20 15:25:03 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.par
View file @ af702851
Release 12.3 par M.70d (nt) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Mon Dec 20 10:59:47 2010 PCBE13225:: Mon Dec 20 15:24:39 2010
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf ApplicationFpga.ncd ApplicationFpga.pcf
...@@ -27,9 +27,9 @@ Slice Logic Utilization: ...@@ -27,9 +27,9 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1% Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 233 out of 92,152 1% Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 217 Number using O6 output only: 222
Number using O5 output only: 14 Number using O5 output only: 14
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used as ROM: 0 Number used as ROM: 0
...@@ -40,17 +40,17 @@ Slice Logic Utilization: ...@@ -40,17 +40,17 @@ Slice Logic Utilization:
Number using O6 output only: 5 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 19 Number used exclusively as route-thrus: 21
Number with same-slice register load: 18 Number with same-slice register load: 20
Number with same-slice carry load: 1 Number with same-slice carry load: 1
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1% Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355 Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12% Number with an unused Flip Flop: 46 out of 355 12%
Number with an unused LUT: 98 out of 355 27% Number with an unused LUT: 91 out of 355 25%
Number of fully used LUT-FF pairs: 213 out of 355 60% Number of fully used LUT-FF pairs: 218 out of 355 61%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -95,8 +95,8 @@ Specific Feature Utilization: ...@@ -95,8 +95,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 20 secs Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
...@@ -106,35 +106,36 @@ WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not ...@@ -106,35 +106,36 @@ WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not
WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal FpGpIo_iob4<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router Starting Router
Phase 1 : 1668 unrouted; REAL time: 23 secs Phase 1 : 1691 unrouted; REAL time: 10 secs
Phase 2 : 1536 unrouted; REAL time: 29 secs Phase 2 : 1560 unrouted; REAL time: 13 secs
Phase 3 : 731 unrouted; REAL time: 32 secs Phase 3 : 730 unrouted; REAL time: 15 secs
Phase 4 : 731 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 43 secs Phase 4 : 730 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Updating file: ApplicationFpga.ncd with current fully routed design. Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Total REAL time to Router completion: 45 secs Total REAL time to Router completion: 22 secs
Total CPU time to Router completion: 45 secs Total CPU time to Router completion: 22 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -152,8 +153,8 @@ Generating Clock Report ...@@ -152,8 +153,8 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|FpGpIo_iob4_2_OBUF_B | | | | | | |FpGpIo_iob4_4_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 85 | 0.144 | 1.648 | | UFG | BUFGMUX_X2Y1| No | 84 | 0.138 | 1.640 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -170,8 +171,8 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -170,8 +171,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.090ns| 7.243ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 0.419ns| 7.914ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.264ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.383ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -182,19 +183,19 @@ Generating Pad Report. ...@@ -182,19 +183,19 @@ Generating Pad Report.
All signals are completely routed. All signals are completely routed.
WARNING:Par:283 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 48 secs Total REAL time to PAR completion: 24 secs
Total CPU time to PAR completion: 48 secs Total CPU time to PAR completion: 24 secs
Peak Memory Usage: 353 MB Peak Memory Usage: 521 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
Timing: Completed - No errors found. Timing: Completed - No errors found.
Number of error messages: 0 Number of error messages: 0
Number of warning messages: 13 Number of warning messages: 14
Number of info messages: 0 Number of info messages: 0
Writing design to file ApplicationFpga.ncd Writing design to file ApplicationFpga.ncd
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.pcf
View file @ af702851
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 10:59:44 2010 // Written by: Map M.70d on Mon Dec 20 15:24:37 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -214,7 +214,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL ...@@ -214,7 +214,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL
BEL "i_DebugRegs/Reg3Value_ob32_3" BEL "i_DebugRegs/Reg3Value_ob32_2" BEL "i_DebugRegs/Reg3Value_ob32_3" BEL "i_DebugRegs/Reg3Value_ob32_2"
BEL "i_DebugRegs/Reg3Value_ob32_1" BEL "i_DebugRegs/Reg3Value_ob32_0" BEL "i_DebugRegs/Reg3Value_ob32_1" BEL "i_DebugRegs/Reg3Value_ob32_0"
BEL "i_Ser2MstWB/Ack_o" BEL "i_Debouncer/DebouncedSignal_oq" BEL BEL "i_Ser2MstWB/Ack_o" BEL "i_Debouncer/DebouncedSignal_oq" BEL
"i_Debouncer/State_q" BEL "FpGpIo_iob4_2_OBUF_BUFG" BEL "i_Debouncer/State_q" BEL "FpGpIo_iob4_4_OBUF_BUFG" BEL
"i_Ser2MstWB/Mshreg_StbI_d3_1" BEL "i_Ser2MstWB/StbI_d3_1" BEL "i_Ser2MstWB/Mshreg_StbI_d3_1" BEL "i_Ser2MstWB/StbI_d3_1" BEL
"i_Ser2MstWB/Mshreg_Rst_xb3_2" BEL "i_Ser2MstWB/Rst_xb3_2" BEL "i_Ser2MstWB/Mshreg_Rst_xb3_2" BEL "i_Ser2MstWB/Rst_xb3_2" BEL
"i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20" BEL "i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20" BEL
...@@ -239,7 +239,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL ...@@ -239,7 +239,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL
"i_Ser2MstWB/Rst_xb3_2_shift25" BEL "i_Ser2MstWB/Rst_xb3_2_shift26" "i_Ser2MstWB/Rst_xb3_2_shift25" BEL "i_Ser2MstWB/Rst_xb3_2_shift26"
BEL "i_Ser2MstWB/Rst_xb3_2_shift27" BEL BEL "i_Ser2MstWB/Rst_xb3_2_shift27" BEL
"i_Ser2MstWB/Rst_xb3_2_shift28" BEL "i_Ser2MstWB/AckI_d31_30" BEL "i_Ser2MstWB/Rst_xb3_2_shift28" BEL "i_Ser2MstWB/AckI_d31_30" BEL
"FpGpIo_iob4<4>" BEL "FpGpIo_iob4<2>" BEL "SysAppClk_ok"; "FpGpIo_iob4<4>" BEL "SysAppClk_ok";
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%; TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
SCHEMATIC END; SCHEMATIC END;
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ptwx
View file @ af702851
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="1.090" best="7.243" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.264" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.419" best="7.914" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.383" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.unroutes
View file @ af702851
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010 Mon Dec 20 15:25:04 2010
All signals are completely routed. All signals are completely routed.
WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings. warnings.
AFpgaProgClk_io_IBUF AFpgaProgClk_io_IBUF
...@@ -19,5 +19,6 @@ WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This desi ...@@ -19,5 +19,6 @@ WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This desi
AFpgaProgM_iob2<0>_IBUF AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF AFpgaProgRdWr_io_IBUF
FpGpIo_iob4<1>_IBUF
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_envsettings.html
View file @ af702851
...@@ -15,17 +15,17 @@ ...@@ -15,17 +15,17 @@
</tr> </tr>
<tr> <tr>
<td>PATHEXT</td> <td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
...@@ -35,13 +35,6 @@ ...@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr> </tr>
<tr> <tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td> <td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
...@@ -515,31 +508,31 @@ ...@@ -515,31 +508,31 @@
</tr> </tr>
<tr> <tr>
<td>CPU Architecture/Speed</td> <td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr> </tr>
<tr> <tr>
<td>Host</td> <td>Host</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
</tr> </tr>
<tr> <tr>
<td>OS Name</td> <td>OS Name</td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
</tr> </tr>
<tr> <tr>
<td>OS Release</td> <td>OS Release</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
</tr> </tr>
</TABLE> </TABLE>
</BODY> </HTML> </BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_guide.ncd
View file @ af702851
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_map.map
View file @ af702851
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'ApplicationFpga' Xilinx Map Application Log File for Design 'ApplicationFpga'
Design Information Design Information
...@@ -11,7 +11,7 @@ Target Device : xc6slx150t ...@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 10:58:56 2010 Mapped Date : Mon Dec 20 15:24:16 2010
Mapping design into LUTs... Mapping design into LUTs...
Running directed packing... Running directed packing...
...@@ -20,54 +20,54 @@ Updating timing models... ...@@ -20,54 +20,54 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 26 secs Total REAL time at the beginning of Placer: 10 secs
Total CPU time at the beginning of Placer: 22 secs Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:22fc166f) REAL time: 34 secs Phase 1.1 Initial Placement Analysis (Checksum:22fc371c) REAL time: 13 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:22fc166f) REAL time: 34 secs Phase 2.7 Design Feasibility Check (Checksum:22fc371c) REAL time: 14 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:22fc166f) REAL time: 34 secs Phase 3.31 Local Placement Optimization (Checksum:22fc371c) REAL time: 14 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:92c41d7) REAL time: 41 secs (Checksum:92c6284) REAL time: 17 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:92c41d7) REAL time: 41 secs Phase 5.36 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:92c41d7) REAL time: 41 secs Phase 6.30 Global Clock Region Assignment (Checksum:92c6284) REAL time: 17 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs Phase 7.3 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs Phase 8.5 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
........................ .............................
..... ........
Phase 9.8 Global Placement (Checksum:3716193a) REAL time: 44 secs Phase 9.8 Global Placement (Checksum:ac53ebd5) REAL time: 19 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3716193a) REAL time: 44 secs Phase 10.5 Local Placement Optimization (Checksum:ac53ebd5) REAL time: 19 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs Phase 11.18 Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs Phase 12.5 Local Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d17f7f67) REAL time: 44 secs Phase 13.34 Placement Validation (Checksum:85180713) REAL time: 19 secs
Total REAL time to Placer completion: 47 secs Total REAL time to Placer completion: 21 secs
Total CPU time to Placer completion: 42 secs Total CPU time to Placer completion: 20 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
...@@ -86,6 +86,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is ...@@ -86,6 +86,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
...@@ -98,16 +100,16 @@ Design Summary ...@@ -98,16 +100,16 @@ Design Summary
Design Summary: Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 11 Number of warnings: 12
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1% Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330 Number used as Flip Flops: 330
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1% Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 233 out of 92,152 1% Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 217 Number using O6 output only: 222
Number using O5 output only: 14 Number using O5 output only: 14
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used as ROM: 0 Number used as ROM: 0
...@@ -118,17 +120,17 @@ Slice Logic Utilization: ...@@ -118,17 +120,17 @@ Slice Logic Utilization:
Number using O6 output only: 5 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 19 Number used exclusively as route-thrus: 21
Number with same-slice register load: 18 Number with same-slice register load: 20
Number with same-slice carry load: 1 Number with same-slice carry load: 1
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1% Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355 Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12% Number with an unused Flip Flop: 46 out of 355 12%
Number with an unused LUT: 98 out of 355 27% Number with an unused LUT: 91 out of 355 25%
Number of fully used LUT-FF pairs: 213 out of 355 60% Number of fully used LUT-FF pairs: 218 out of 355 61%
Number of unique control sets: 10 Number of unique control sets: 10
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 25 out of 184,304 1% to control set restrictions: 25 out of 184,304 1%
...@@ -170,11 +172,11 @@ Specific Feature Utilization: ...@@ -170,11 +172,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.47 Average Fanout of Non-Clock Nets: 4.49
Peak Memory Usage: 380 MB Peak Memory Usage: 583 MB
Total REAL time to MAP completion: 49 secs Total REAL time to MAP completion: 21 secs
Total CPU time to MAP completion: 43 secs Total CPU time to MAP completion: 21 secs
Mapping completed. Mapping completed.
See MAP report file "ApplicationFpga_map.mrp" for details. See MAP report file "ApplicationFpga_map.mrp" for details.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_map.mrp
View file @ af702851
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'ApplicationFpga' Xilinx Mapping Report File for Design 'ApplicationFpga'
Design Information Design Information
...@@ -11,21 +11,21 @@ Target Device : xc6slx150t ...@@ -11,21 +11,21 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 10:58:56 2010 Mapped Date : Mon Dec 20 15:24:16 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 11 Number of warnings: 12
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1% Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330 Number used as Flip Flops: 330
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1% Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 233 out of 92,152 1% Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 217 Number using O6 output only: 222
Number using O5 output only: 14 Number using O5 output only: 14
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used as ROM: 0 Number used as ROM: 0
...@@ -36,17 +36,17 @@ Slice Logic Utilization: ...@@ -36,17 +36,17 @@ Slice Logic Utilization:
Number using O6 output only: 5 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 19 Number used exclusively as route-thrus: 21
Number with same-slice register load: 18 Number with same-slice register load: 20
Number with same-slice carry load: 1 Number with same-slice carry load: 1
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1% Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355 Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12% Number with an unused Flip Flop: 46 out of 355 12%
Number with an unused LUT: 98 out of 355 27% Number with an unused LUT: 91 out of 355 25%
Number of fully used LUT-FF pairs: 213 out of 355 60% Number of fully used LUT-FF pairs: 218 out of 355 61%
Number of unique control sets: 10 Number of unique control sets: 10
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 25 out of 184,304 1% to control set restrictions: 25 out of 184,304 1%
...@@ -88,11 +88,11 @@ Specific Feature Utilization: ...@@ -88,11 +88,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.47 Average Fanout of Non-Clock Nets: 4.49
Peak Memory Usage: 380 MB Peak Memory Usage: 583 MB
Total REAL time to MAP completion: 49 secs Total REAL time to MAP completion: 21 secs
Total CPU time to MAP completion: 43 secs Total CPU time to MAP completion: 21 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -131,6 +131,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is ...@@ -131,6 +131,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
...@@ -141,13 +143,13 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is ...@@ -141,13 +143,13 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
Section 3 - Informational Section 3 - Informational
------------------------- -------------------------
INFO:LIT:243 - Logical network AFpgaProgM_iob2<1>_IBUF has no load. INFO:LIT:243 - Logical network AFpgaProgM_iob2<1>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 10 more times for the INFO:LIT:395 - The above info message is repeated 11 more times for the
following (max. 5 shown): following (max. 5 shown):
AFpgaProgM_iob2<0>_IBUF, AFpgaProgM_iob2<0>_IBUF,
FpGpIo_iob4<1>_IBUF,
AFpgaProgD_iob8<6>_IBUF, AFpgaProgD_iob8<6>_IBUF,
AFpgaProgD_iob8<3>_IBUF, AFpgaProgD_iob8<3>_IBUF,
AFpgaProgD_iob8<2>_IBUF, AFpgaProgD_iob8<2>_IBUF
AFpgaProgD_iob8<1>_IBUF
To see the details of these info messages, please use the -detail switch. To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew INFO:LIT:244 - All of the single ended outputs in this design are using slew
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_map.ncd
View file @ af702851
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_map.xrpt
View file @ af702851
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Mon Dec 20 10:59:46 2010"> <application stringID="Map" timeStamp="Mon Dec 20 15:24:38 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/> <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -74,9 +70,9 @@ ...@@ -74,9 +70,9 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="239"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="244">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="14"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="14"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="217"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="222"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
...@@ -119,10 +115,10 @@ ...@@ -119,10 +115,10 @@
<section stringID="MAP_DESIGN_SUMMARY"> <section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="11"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="12"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="389500"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="597428"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="49 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="21 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="43 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="21 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="330"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="330">
...@@ -131,9 +127,9 @@ ...@@ -131,9 +127,9 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="257"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="264">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="14"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="14"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="217"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="222"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
...@@ -148,21 +144,21 @@ ...@@ -148,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="1"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="18"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="20"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="18"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="20"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="108"> <item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="108">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="4"/> <item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="5"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="100"/> <item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="99"/>
</item> </item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="355"> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="355">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="44"/> <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="46"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="98"/> <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="91"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="213"/> <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="218"/>
</item> </item>
</section> </section>
<section stringID="MAP_IOB_REPORTING"> <section stringID="MAP_IOB_REPORTING">
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_ngdbuild.xrpt
View file @ af702851
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 10:58:52 2010"> <application stringID="NgdBuild" timeStamp="Mon Dec 20 15:24:14 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/> <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -65,7 +61,7 @@ ...@@ -65,7 +61,7 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY"> <section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/> <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="11"/> <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="12"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/> <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/> <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section> </section>
...@@ -78,15 +74,16 @@ ...@@ -78,15 +74,16 @@
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="147"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="147"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="10"/> <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="202"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="206"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/>
...@@ -109,8 +106,9 @@ ...@@ -109,8 +106,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="202"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="206"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/>
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_pad.csv
View file @ af702851
#Release 12.3 - par M.70d (nt) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Mon Dec 20 11:00:35 2010 #Mon Dec 20 15:25:03 2010
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_pad.txt
View file @ af702851
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010 Mon Dec 20 15:25:03 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_summary.xml
View file @ af702851
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="2"> <DesignSummary rev="10">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_xst.xrpt
View file @ af702851
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Mon Dec 20 10:51:04 2010"> <application stringID="Xst" timeStamp="Mon Dec 20 15:24:05 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/> <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -159,7 +155,7 @@ ...@@ -159,7 +155,7 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="ApplicationFpga.ngc"/> <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="ApplicationFpga.ngc"/>
</section> </section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE"> <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="268"> <item dataType="int" stringID="XST_BELS" value="273">
<item dataType="int" stringID="XST_GND" value="1"/> <item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="3"/> <item dataType="int" stringID="XST_INV" value="3"/>
<item dataType="int" stringID="XST_LUT1" value="15"/> <item dataType="int" stringID="XST_LUT1" value="15"/>
...@@ -167,8 +163,9 @@ ...@@ -167,8 +163,9 @@
<item dataType="int" stringID="XST_LUT3" value="2"/> <item dataType="int" stringID="XST_LUT3" value="2"/>
<item dataType="int" stringID="XST_LUT4" value="2"/> <item dataType="int" stringID="XST_LUT4" value="2"/>
<item dataType="int" stringID="XST_LUT5" value="6"/> <item dataType="int" stringID="XST_LUT5" value="6"/>
<item dataType="int" stringID="XST_LUT6" value="202"/> <item dataType="int" stringID="XST_LUT6" value="206"/>
<item dataType="int" stringID="XST_MUXCY" value="15"/> <item dataType="int" stringID="XST_MUXCY" value="15"/>
<item dataType="int" stringID="XST_MUXF7" value="1"/>
<item dataType="int" stringID="XST_VCC" value="1"/> <item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="16"/> <item dataType="int" stringID="XST_XORCY" value="16"/>
</item> </item>
...@@ -186,8 +183,8 @@ ...@@ -186,8 +183,8 @@
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1"> <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/> <item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="12"> <item dataType="int" stringID="XST_IO_BUFFERS" value="11">
<item dataType="int" stringID="XST_IBUF" value="6"/> <item dataType="int" stringID="XST_IBUF" value="5"/>
<item dataType="int" stringID="XST_OBUF" value="6"/> <item dataType="int" stringID="XST_OBUF" value="6"/>
</item> </item>
</section> </section>
...@@ -195,17 +192,17 @@ ...@@ -195,17 +192,17 @@
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/> <item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="330"/> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="330"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="240"/> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="244"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="235"/> <item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="239"/>
<item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="5"/> <item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="5"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="5"/> <item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="5"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="381"/> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="385"/>
<item AVAILABLE="381" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="51"/> <item AVAILABLE="385" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="55"/>
<item AVAILABLE="381" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="141"/> <item AVAILABLE="385" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="141"/>
<item AVAILABLE="381" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="189"/> <item AVAILABLE="385" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="189"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="11"/> <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="11"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="23"/> <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="23"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="12"/> <item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="11"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="1"/> <item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="1"/>
</section> </section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY"> <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
......
trunk/firmware/XilinxISE/ApplicationFpga/_ngo/netlist.lst
View file @ af702851
C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.ngc 1292838673 C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.ngc 1292855051
OK OK
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/bitgen.xmsgs
View file @ af702851
...@@ -5,40 +5,43 @@ ...@@ -5,40 +5,43 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="Bitgen" num="244" delta="new" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup. <msg type="warning" file="Bitgen" num="244" delta="old" >A StartupClk setting other than JtagClk is being used to generate a bitstream in IEEE1532 format. The IEEE1532 option implies that JTAG configuration will be used. Using a StartupClk setting other than JtagClk could prevent proper device startup.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">FpGpIo_iob4&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/map.xmsgs
View file @ af702851
...@@ -5,67 +5,70 @@ ...@@ -5,67 +5,70 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg> has no load. <msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg> has no load.
</msg> </msg>
<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">10</arg> more times for the following (max. 5 shown): <msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">11</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">AFpgaProgM_iob2&lt;0&gt;_IBUF, <arg fmt="%s" index="3">AFpgaProgM_iob2&lt;0&gt;_IBUF,
FpGpIo_iob4&lt;1&gt;_IBUF,
AFpgaProgD_iob8&lt;6&gt;_IBUF, AFpgaProgD_iob8&lt;6&gt;_IBUF,
AFpgaProgD_iob8&lt;3&gt;_IBUF, AFpgaProgD_iob8&lt;3&gt;_IBUF,
AFpgaProgD_iob8&lt;2&gt;_IBUF, AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>
AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch. To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg> </msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set. <msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg> </msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. <msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg> </msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius) <msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg> </msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts) <msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg> </msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp). <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg> </msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design. <msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">FpGpIo_iob4&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design. <msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="old" >The signal &lt;<arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/ngdbuild.xmsgs
View file @ af702851
...@@ -5,37 +5,40 @@ ...@@ -5,37 +5,40 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;0&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;0&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;6&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">FpGpIo_iob4&lt;1&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;3&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;6&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;2&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;3&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;1&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;2&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;0&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;1&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgClk_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgD_iob8&lt;0&gt;</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgCsi_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgClk_io</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgRdWr_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgCsi_io</arg>&apos; has no legal driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="new" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgInit_io</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgRdWr_io</arg>&apos; has no legal driver
</msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgInit_io</arg>&apos; has no legal driver
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/par.xmsgs
View file @ af702851
...@@ -5,44 +5,47 @@ ...@@ -5,44 +5,47 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgClk_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgRdWr_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;2&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;3&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgD_iob8&lt;6&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgCsi_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">FpGpIo_iob4&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgInit_io_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;0&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg> </msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">11</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. <msg type="warning" file="Par" num="288" delta="old" >The signal <arg fmt="%s" index="1">AFpgaProgM_iob2&lt;1&gt;_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="ParHelpers" num="361" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg> </msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">11</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings. <msg type="warning" file="Par" num="283" delta="old" >There are <arg fmt="%d" index="1">12</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg> </msg>
......
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/pn_parser.xmsgs
View file @ af702851
...@@ -8,5 +8,8 @@ ...@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
</messages> </messages>
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/trce.xmsgs
View file @ af702851
...@@ -5,9 +5,9 @@ ...@@ -5,9 +5,9 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> <msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> <msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages> </messages>
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/xst.xmsgs
View file @ af702851
...@@ -11,31 +11,31 @@ ...@@ -11,31 +11,31 @@
<msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 20: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined. <msg type="warning" file="HDLCompiler" num="572" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 20: Macro &lt;<arg fmt="%s" index="1">dly</arg>&gt; is redefined.
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 104: Assignment to <arg fmt="%s" index="1">DebugReg0</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 105: Assignment to <arg fmt="%s" index="1">DebugReg0</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 105: Assignment to <arg fmt="%s" index="1">DebugReg1</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 106: Assignment to <arg fmt="%s" index="1">DebugReg1</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 106: Assignment to <arg fmt="%s" index="1">DebugReg2</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 107: Assignment to <arg fmt="%s" index="1">DebugReg2</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 107: Assignment to <arg fmt="%s" index="1">DebugReg3</arg> ignored, since the identifier is never used <msg type="warning" file="HDLCompiler" num="1127" delta="old" >"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 108: Assignment to <arg fmt="%s" index="1">DebugReg3</arg> ignored, since the identifier is never used
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">94</arg>: Output port &lt;<arg fmt="%s" index="3">Reg0Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Output port &lt;<arg fmt="%s" index="3">Reg0Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">94</arg>: Output port &lt;<arg fmt="%s" index="3">Reg1Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Output port &lt;<arg fmt="%s" index="3">Reg1Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">94</arg>: Output port &lt;<arg fmt="%s" index="3">Reg2Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Output port &lt;<arg fmt="%s" index="3">Reg2Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">94</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/applicationfpga.v</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_DebugRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">Adr_ib21&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Adr_ib21&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/ApplicationFpga/applicationfpga.bgn
View file @ af702851
Release 12.3 - Bitgen M.70d (nt) Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\. C:\Xilinx\12.3\ISE_DS\ISE\.
...@@ -6,9 +6,9 @@ C:\Xilinx\12.3\ISE_DS\ISE\. ...@@ -6,9 +6,9 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
speed -3 speed -3
Opened constraints file ApplicationFpga.pcf. Opened constraints file ApplicationFpga.pcf.
Mon Dec 20 11:02:27 2010 Mon Dec 20 15:25:21 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ApplicationFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ApplicationFpga.ncd
WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to
generate a bitstream in IEEE1532 format. The IEEE1532 option implies that generate a bitstream in IEEE1532 format. The IEEE1532 option implies that
...@@ -143,13 +143,15 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is ...@@ -143,13 +143,15 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 11 warnings. Please see the previously displayed DRC detected 0 errors and 12 warnings. Please see the previously displayed
individual error or warning messages for more details. individual error or warning messages for more details.
Creating bit map... Creating bit map...
Saving bit stream in "applicationfpga.bit". Saving bit stream in "applicationfpga.bit".
......
trunk/firmware/XilinxISE/ApplicationFpga/applicationfpga.drc
View file @ af702851
Release 12.3 Drc M.70d (nt) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:02:27 2010 Mon Dec 20 15:25:21 2010
drc -z ApplicationFpga.ncd ApplicationFpga.pcf drc -z ApplicationFpga.ncd ApplicationFpga.pcf
...@@ -21,11 +21,13 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is ...@@ -21,11 +21,13 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design. incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 11 warnings. Please see the previously displayed DRC detected 0 errors and 12 warnings. Please see the previously displayed
individual error or warning messages for more details. individual error or warning messages for more details.
trunk/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.projectmgr
View file @ af702851
<?xml version="1.0" encoding="utf-8"?> <?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.--> <!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.--> <!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
...@@ -23,13 +23,13 @@ ...@@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem></SelectedItem> <SelectedItem/>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a2000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a2000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem/>
</ItemView> </ItemView>
<ItemView guiview="File" > <ItemView guiview="File" >
<ClosedNodes> <ClosedNodes>
...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem>AddrDecoderWBApp.v</CurrentItem>
</ItemView> </ItemView>
<ItemView guiview="Library" > <ItemView guiview="Library" >
<ClosedNodes> <ClosedNodes>
...@@ -57,19 +57,18 @@ ...@@ -57,19 +57,18 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode> <ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode> <ClosedNode>Synthesize - XST</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem></SelectedItem> <SelectedItem>Configure Target Device</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a2000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem>Configure Target Device</CurrentItem>
</ItemView> </ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView> <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView> <CurrentView>Implementation</CurrentView>
......
trunk/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport
View file @ af702851
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2010-12-20T10:52:05</DateModified> <DateModified>2010-12-20T14:11:35</DateModified>
<ModuleName>ApplicationFpga</ModuleName> <ModuleName>ApplicationFpga</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/ApplicationFpga/par_usage_statistics.html
View file @ af702851
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>393</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>396</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1617</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1640</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1617</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1640</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>1606</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>1622</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>23.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>10.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>32.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>15.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>43.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>44.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>44.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>44.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>44.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>44.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>45.0 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>22.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>1.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.1</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>12.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>11.6</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>54.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>40.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0178</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0180</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/ApplicationFpga/webtalk.log
View file @ af702851
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=E95F264691074EB59A186285E0ED1DCA ProjectID=E95F264691074EB59A186285E0ED1DCA
ProjectIteration=1 ProjectIteration=5
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T11:03:12. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T15:25:46. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/ApplicationFpga/webtalk_pn.xml
View file @ af702851
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Dec 20 11:02:17 2010"> <application name="pn" timeStamp="Mon Dec 20 15:25:16 2010">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="project"/> <property name="ProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="project"/>
<property name="ProjectIteration" value="1" type="project"/> <property name="ProjectIteration" value="5" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-20T10:26:08" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-20T10:26:08" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-20T10:26:08" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-20T10:26:08" type="design"/>
<property name="PROP_intWbtProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="design"/> <property name="PROP_intWbtProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="design"/>
<property name="PROP_intWbtProjectIteration" value="1" type="process"/> <property name="PROP_intWbtProjectIteration" value="5" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ af702851
...@@ -15,8 +15,8 @@ Checking Constraint Associations... ...@@ -15,8 +15,8 @@ Checking Constraint Associations...
Done... Done...
Checking expanded design ... Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N456' has no driver WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:452 - logical net 'N458' has no driver WARNING:NgdBuild:452 - logical net 'N454' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
...@@ -41,10 +41,10 @@ NGDBUILD Design Results Summary: ...@@ -41,10 +41,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 14 Number of warnings: 14
Total memory usage is 155980 kilobytes Total memory usage is 154956 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ af702851
...@@ -81,3 +81,15 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -81,3 +81,15 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ af702851
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 08:27:29 2010 Mon Dec 20 13:48:21 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
...@@ -99,7 +99,7 @@ AB25|||GND|||||||||||| ...@@ -99,7 +99,7 @@ AB25|||GND||||||||||||
AB26||IOBS|IO_L49N_M1DQ11_1|UNUSED||1||||||||| AB26||IOBS|IO_L49N_M1DQ11_1|UNUSED||1|||||||||
AC1|PcbRev_ib8<3>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| AC1|PcbRev_ib8<3>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AC2|PcbRev_ib8<4>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| AC2|PcbRev_ib8<4>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AC3|PllDdsRefSel_o|IOB|IO_L8N_3|OUTPUT|LVCMOS25*|3|12|||||UNLOCATED|NO|NONE| AC3|AFpgaProgDone_io|IOB|IO_L8N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
AC4|SysAppSlow_iob2<1>|IOB|IO_L1N_VREF_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE| AC4|SysAppSlow_iob2<1>|IOB|IO_L1N_VREF_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
AC5|PllFmc1Reset_orn|IOB|IO_L61P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE| AC5|PllFmc1Reset_orn|IOB|IO_L61P_2|OUTPUT|LVCMOS33|2|12|||||LOCATED|NO|NONE|
AC6|PllFmc1Sdo_i|IOB|IO_L53N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| AC6|PllFmc1Sdo_i|IOB|IO_L53N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
...@@ -597,7 +597,7 @@ U3|FpLed_onb8<5>|IOB|IO_L10N_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| ...@@ -597,7 +597,7 @@ U3|FpLed_onb8<5>|IOB|IO_L10N_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE| U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U6|||VCCAUX||||||||2.5|||| U6|||VCCAUX||||||||2.5||||
U7||IOBM|IO_L31P_3|UNUSED||3||||||||| U7|PllDdsRefSel_o|IOB|IO_L31P_3|OUTPUT|LVCMOS25*|3|12|||||UNLOCATED|NO|NONE|
U8|AFpgaProgInit_io|IOB|IO_L18N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE| U8|AFpgaProgInit_io|IOB|IO_L18N_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U9||IOBM|IO_L18P_3|UNUSED||3||||||||| U9||IOBM|IO_L18P_3|UNUSED||3|||||||||
U10|||VCCINT||||||||1.2|||| U10|||VCCINT||||||||1.2||||
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ af702851
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 08:26:52 2010 // Written by: Map M.70d on Mon Dec 20 13:47:47 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -127,6 +127,7 @@ COMP "FpLed_onb8<5>" LOCATE = SITE "U3" LEVEL 1; ...@@ -127,6 +127,7 @@ COMP "FpLed_onb8<5>" LOCATE = SITE "U3" LEVEL 1;
COMP "FpLed_onb8<6>" LOCATE = SITE "U4" LEVEL 1; COMP "FpLed_onb8<6>" LOCATE = SITE "U4" LEVEL 1;
COMP "FpLed_onb8<7>" LOCATE = SITE "T4" LEVEL 1; COMP "FpLed_onb8<7>" LOCATE = SITE "T4" LEVEL 1;
COMP "FlashSFpgaClk_ok" LOCATE = SITE "AE24" LEVEL 1; COMP "FlashSFpgaClk_ok" LOCATE = SITE "AE24" LEVEL 1;
COMP "AFpgaProgDone_io" LOCATE = SITE "AC3" LEVEL 1;
COMP "Fmc1PGC2M_in" LOCATE = SITE "W1" LEVEL 1; COMP "Fmc1PGC2M_in" LOCATE = SITE "W1" LEVEL 1;
COMP "DdrBA_ob3<0>" LOCATE = SITE "R20" LEVEL 1; COMP "DdrBA_ob3<0>" LOCATE = SITE "R20" LEVEL 1;
COMP "DdrBA_ob3<1>" LOCATE = SITE "R21" LEVEL 1; COMP "DdrBA_ob3<1>" LOCATE = SITE "R21" LEVEL 1;
...@@ -490,6 +491,33 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -490,6 +491,33 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL "i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL "i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL "i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_25" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_24" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_23" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_22" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_21" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_20" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_19" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_18" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_17" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_16" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_15" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_14" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_13" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_12" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_11" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_10" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_9" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_8" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_7" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_6" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_5" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_4" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_3" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_2" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_1" BEL
"i_Core/i_WriteCycleMonostable/Counter_c_0" BEL
"i_Core/i_WriteCycleMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL "i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL "i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL "i_Core/i_Debouncer/Counter_c_13" BEL
...@@ -885,10 +913,11 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -885,10 +913,11 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/i_SpiMasterWB/SS_onb32_3" BEL "i_Core/i_SpiMasterWB/SS_onb32_3" BEL
"i_Core/i_SpiMasterWB/SS_onb32_6" BEL "i_Core/i_SpiMasterWB/SS_onb32_6" BEL
"i_Core/i_SpiMasterWB/SS_onb32_7" BEL "i_Core/i_SpiMasterWB/SS_onb32_7" BEL
"i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/i_SpiMasterWB/SS_onb32_8" BEL "i_Core/WriteCycle" BEL
"i_Core/i_VmeInterface/state_FSM_FFd1" BEL "i_Core/i_VmeInterface/state_FSM_FFd1" BEL
"i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL "i_Core/i_VmeAccessMonostable/SynchOutput_oq" BEL
"i_Core/i_ClearMonostable/SynchOutput_oq" BEL "i_Core/i_ClearMonostable/SynchOutput_oq" BEL
"i_Core/i_WriteCycleMonostable/SynchOutput_oq" BEL
"i_Core/i_Debouncer/DebouncedSignal_oq" BEL "i_Core/i_Debouncer/DebouncedSignal_oq" BEL
"i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int" "i_Core/i_Debouncer/State_q" BEL "i_Core/i_InterruptManager/ready4int"
BEL "i_Core/i_InterruptManager/fifo_empty" BEL BEL "i_Core/i_InterruptManager/fifo_empty" BEL
...@@ -973,10 +1002,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL ...@@ -973,10 +1002,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL "i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL "i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL "i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL "i_Core/i_Slv2SerWB/AckI_xb3_0" BEL
"i_Core/i_WriteCycleMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_WriteCycleMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL "PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL "PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL "i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ af702851
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.429" best="7.904" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.225" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.826" best="3.507" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.468" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.224" best="8.109" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.342" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.902" best="3.431" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.392" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ af702851
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ af702851
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 08:27:29 2010 Mon Dec 20 13:48:22 2010
All signals are completely routed. All signals are completely routed.
WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings. warnings.
AFpgaProgClk_io_IBUF AFpgaProgClk_io_IBUF
...@@ -15,6 +15,7 @@ WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This desi ...@@ -15,6 +15,7 @@ WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This desi
AFpgaProgD_iob8<2>_IBUF AFpgaProgD_iob8<2>_IBUF
AFpgaProgD_iob8<3>_IBUF AFpgaProgD_iob8<3>_IBUF
AFpgaProgD_iob8<6>_IBUF AFpgaProgD_iob8<6>_IBUF
AFpgaProgDone_io_IBUF
AFpgaProgInit_io_IBUF AFpgaProgInit_io_IBUF
AFpgaProgM_iob2<0>_IBUF AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF AFpgaProgM_iob2<1>_IBUF
...@@ -40,6 +41,8 @@ WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This desi ...@@ -40,6 +41,8 @@ WARNING:ParHelpers:361 - There are 47 loadless signals in this design. This desi
Sfp2LoS_i_IBUF Sfp2LoS_i_IBUF
Sfp2ModeDef0_i_IBUF Sfp2ModeDef0_i_IBUF
Sfp2TxFault_i_IBUF Sfp2TxFault_i_IBUF
Switch_ib2<0>_IBUF
Switch_ib2<1>_IBUF
TempIdDQ_io_IBUF TempIdDQ_io_IBUF
VmeAm_ib6<1>_IBUF VmeAm_ib6<1>_IBUF
VmeAm_ib6<2>_IBUF VmeAm_ib6<2>_IBUF
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ut
View file @ af702851
-w -w
-g DebugBitstream:No -g DebugBitstream:No
-g Binary:no -g Binary:yes
-b
-g IEEE1532:Yes
-g CRC:Enable -g CRC:Enable
-g Reset_on_err:No -g Reset_on_err:No
-g ConfigRate:2 -g ConfigRate:2
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ af702851
#Release 12.3 - par M.70d (nt64) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Mon Dec 20 08:27:29 2010 #Mon Dec 20 13:48:21 2010
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
...@@ -99,7 +99,7 @@ AB25,,,GND,,,,,,,,,,,, ...@@ -99,7 +99,7 @@ AB25,,,GND,,,,,,,,,,,,
AB26,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,, AB26,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,,
AC1,PcbRev_ib8<3>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, AC1,PcbRev_ib8<3>,IOB,IO_L34N_M3UDQSN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AC2,PcbRev_ib8<4>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, AC2,PcbRev_ib8<4>,IOB,IO_L34P_M3UDQS_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AC3,PllDdsRefSel_o,IOB,IO_L8N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, AC3,AFpgaProgDone_io,IOB,IO_L8N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
AC4,SysAppSlow_iob2<1>,IOB,IO_L1N_VREF_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, AC4,SysAppSlow_iob2<1>,IOB,IO_L1N_VREF_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
AC5,PllFmc1Reset_orn,IOB,IO_L61P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE, AC5,PllFmc1Reset_orn,IOB,IO_L61P_2,OUTPUT,LVCMOS33,2,12,,,,,LOCATED,NO,NONE,
AC6,PllFmc1Sdo_i,IOB,IO_L53N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, AC6,PllFmc1Sdo_i,IOB,IO_L53N_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE,
...@@ -597,7 +597,7 @@ U3,FpLed_onb8<5>,IOB,IO_L10N_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, ...@@ -597,7 +597,7 @@ U3,FpLed_onb8<5>,IOB,IO_L10N_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE, U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U6,,,VCCAUX,,,,,,,,2.5,,,, U6,,,VCCAUX,,,,,,,,2.5,,,,
U7,,IOBM,IO_L31P_3,UNUSED,,3,,,,,,,,, U7,PllDdsRefSel_o,IOB,IO_L31P_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE,
U8,AFpgaProgInit_io,IOB,IO_L18N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE, U8,AFpgaProgInit_io,IOB,IO_L18N_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U9,,IOBM,IO_L18P_3,UNUSED,,3,,,,,,,,, U9,,IOBM,IO_L18P_3,UNUSED,,3,,,,,,,,,
U10,,,VCCINT,,,,,,,,1.2,,,, U10,,,VCCINT,,,,,,,,1.2,,,,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ af702851
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 08:27:29 2010 Mon Dec 20 13:48:21 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
...@@ -100,7 +100,7 @@ Pinout by Pin Number: ...@@ -100,7 +100,7 @@ Pinout by Pin Number:
|AB26 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | | |AB26 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | |
|AC1 |PcbRev_ib8<3> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |AC1 |PcbRev_ib8<3> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|AC2 |PcbRev_ib8<4> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |AC2 |PcbRev_ib8<4> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|AC3 |PllDdsRefSel_o |IOB |IO_L8N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | |AC3 |AFpgaProgDone_io |IOB |IO_L8N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|AC4 |SysAppSlow_iob2<1> |IOB |IO_L1N_VREF_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |AC4 |SysAppSlow_iob2<1> |IOB |IO_L1N_VREF_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|AC5 |PllFmc1Reset_orn |IOB |IO_L61P_2 |OUTPUT |LVCMOS33 |2 |12 | | | | |LOCATED |NO |NONE | |AC5 |PllFmc1Reset_orn |IOB |IO_L61P_2 |OUTPUT |LVCMOS33 |2 |12 | | | | |LOCATED |NO |NONE |
|AC6 |PllFmc1Sdo_i |IOB |IO_L53N_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | |AC6 |PllFmc1Sdo_i |IOB |IO_L53N_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE |
...@@ -598,7 +598,7 @@ Pinout by Pin Number: ...@@ -598,7 +598,7 @@ Pinout by Pin Number:
|U4 |FpLed_onb8<6> |IOB |IO_L10P_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE | |U4 |FpLed_onb8<6> |IOB |IO_L10P_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U5 |AFpgaProgD_iob8<4> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |U5 |AFpgaProgD_iob8<4> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U6 | | |VCCAUX | | | | | | | |2.5 | | | | |U6 | | |VCCAUX | | | | | | | |2.5 | | | |
|U7 | |IOBM |IO_L31P_3 |UNUSED | |3 | | | | | | | | | |U7 |PllDdsRefSel_o |IOB |IO_L31P_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE |
|U8 |AFpgaProgInit_io |IOB |IO_L18N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |U8 |AFpgaProgInit_io |IOB |IO_L18N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U9 | |IOBM |IO_L18P_3 |UNUSED | |3 | | | | | | | | | |U9 | |IOBM |IO_L18P_3 |UNUSED | |3 | | | | | | | | |
|U10 | | |VCCINT | | | | | | | |1.2 | | | | |U10 | | |VCCINT | | | | | | | |1.2 | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ af702851
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="17"> <DesignSummary rev="21">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ af702851
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292829930 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292849212
OK OK
trunk/firmware/XilinxISE/SystemFpga/sfpga.isc 0 → 100644
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trunk/firmware/XilinxISE/SystemFpga/sfpga.rbt 0 → 100644
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trunk/hdl/design/ApplicationFpga.v
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trunk/hdl/design/SystemFpga.v
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trunk/hdl/design/XilinxWrappers/SFpga.v
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