Merge branch 'tg-gc_argb_led_drv' into 'master'

gc argb led drv See merge request !67

Merge branch 'tg-gc_argb_led_drv' into 'master'
gc argb led drv See merge request !67
038e1aad · Tristan Gingold · d62e22e0 · 304a4819 · 038e1aad · 038e1aad
Commit 038e1aad authored May 03, 2024 by Tristan Gingold
6 changed files
--- a/README.md
+++ b/README.md
@@ -84,6 +84,9 @@ In [modules/common](modules/common) there are general purpose cores:
 * Module [gc_bicolor_led_ctrl](modules/common/gc_bicolor_led_ctrl.vhd)
  controls multiple bicolor leds, including the intensity.

+* Module [gc_argb_led_drv](modules/common/gc_argb_led_drv.vhd)
+  controls one or several ARGB (aka intelligent) leds.
+
 * Module [gc_big_adder](modules/common/gc_big_adder.vhd) provides a pipelined
  adder for wide numbers.


--- a/modules/axi/mpsoc_int_gen/mpsoc_int_gen.vhd
+++ b/modules/axi/mpsoc_int_gen/mpsoc_int_gen.vhd
@@ -85,7 +85,7 @@ begin
  S_AXI_awsize <= "010";

  --  Normal Non-cacheable Non-bufferable
-  S_AXI_awcache <= "0010";
+  S_AXI_awcache <= "0001"; -- 0001 is device, 0000 is strongly-ordered

  --  Reuse the same id.
  S_AXI_awid <= "000000";

--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -42,4 +42,5 @@ files = [
    "gc_async_counter_diff.vhd",
    "gc_sync_word_wr.vhd",
    "gc_sync_word_rd.vhd",
+    "gc_argb_led_drv.vhd",
 ];
--- a/modules/common/gc_argb_led_drv.vhd
+++ b/modules/common/gc_argb_led_drv.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- Project    : General Cores Collection library
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_argb_led_drv
+--
+-- description: Driver for argb (or intelligent) led like ws2812b
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2024
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gc_argb_led_drv is
+  generic (
+    g_clk_freq : natural
+  );
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    --  Input: color + valid bit.
+    --  The input is read when both ready_o and valid_i are set.
+    --  It is then transmitted, and during the transmission, ready_o
+    --  is false.
+    g_i     : in std_logic_vector(7 downto 0);
+    r_i     : in std_logic_vector(7 downto 0);
+    b_i     : in std_logic_vector(7 downto 0);
+    valid_i : in std_logic;
+
+    --  Output to the first led.
+    dout_o  : out std_logic;
+
+    --  Set when ready to use the input.
+    ready_o : out std_logic;
+
+    --  If no new inputs are valid for 50us while ready_o is set,
+    --  res_o raises to indicate the led are reset.  The next input
+    --  will be used by the first led.
+    res_o   : out std_logic
+  );
+end gc_argb_led_drv;
+
+architecture arch of gc_argb_led_drv is
+  constant C_T0H : natural := g_clk_freq * 8  / 20_000_000 - 1; -- 0.4us
+  constant C_T0L : natural := g_clk_freq * 17 / 20_000_000 - 1; -- 0.85us
+
+  constant C_T1H : natural := g_clk_freq * 16 / 20_000_000 - 1; -- 0.8us
+  constant C_T1L : natural := g_clk_freq * 9  / 20_000_000 - 1; -- 0.45us
+
+  signal frame : std_logic_vector(23 downto 0);
+  signal counter : natural range 0 to C_T0L;
+  subtype t_reset is natural range 0 to g_clk_freq * 5 / 100_000 - 1;
+  signal res_counter : t_reset;
+  signal shift_cnt : natural range 0 to 23;
+  signal hi_lo : std_logic;
+  signal tx : std_logic;
+  signal msb : std_logic;
+begin
+  ready_o <= not tx;
+
+  msb <= frame(23);
+  dout_o <= hi_lo;
+
+  process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        res_o <= '0';
+        res_counter <= 0;
+      else
+        if tx = '1' then
+          res_counter <= 0;
+          res_o <= '0';
+        elsif res_counter = t_reset'high then
+          res_o <= '1';
+        else
+          res_counter <= res_counter + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        tx <= '0';
+        frame <= (others => '0');
+        hi_lo <= '0';
+      else
+        if tx = '0' then
+          if valid_i = '1' then
+            --  Note: the order depends on the manufacturer.
+            frame <= r_i & g_i & b_i;
+            tx <= '1';
+            shift_cnt <= 0;
+            counter <= 0;
+            hi_lo <= '1';
+          end if;
+        else
+          if hi_lo = '1'
+           and ((msb = '1' and counter = C_T1H) or (msb = '0' and counter = C_T0H))
+          then
+            hi_lo <= '0';
+            counter <= 0;
+          elsif hi_lo = '0'
+            and ((msb = '1' and counter = C_T1L) or (msb = '0' and counter = C_T0L))
+          then
+            if shift_cnt = 23 then
+              tx <= '0';
+            else
+              shift_cnt <= shift_cnt + 1;
+              frame <= frame(22 downto 0) & '0';
+              counter <= 0;
+              hi_lo <= '1';
+            end if;
+          else
+            counter <= counter + 1;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+end arch;
\ No newline at end of file
--- a/testbench/common/gc_argb_led_drv/Manifest.py
+++ b/testbench/common/gc_argb_led_drv/Manifest.py
+action   = "simulation"
+sim_tool = "ghdl"
+
+target      = "xilinx"
+syn_device  = "xc6slx45t"
+
+sim_top = "gc_argb_led_drv_tb"
+
+files = [
+        "gc_argb_led_drv_tb.vhd",
+    ]
+
+modules = {
+    "local" :  [
+        "../../../",
+    ],
+}
--- a/testbench/common/gc_argb_led_drv/gc_argb_led_drv_tb.vhd
+++ b/testbench/common/gc_argb_led_drv/gc_argb_led_drv_tb.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- Project    : General Cores Collection library
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_argb_led_drv
+--
+-- description: Driver for argb (or intelligent) led like ws2812b
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2024
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gc_argb_led_drv_tb is
+end;
+
+architecture arch of gc_argb_led_drv_tb is
+  constant C_CLK_FREQ : natural := 62_500_000;
+  signal clk   : std_logic := '0';
+  signal rst_n : std_logic := '0';
+  signal b_g   : std_logic_vector(7 downto 0);
+  signal b_r   : std_logic_vector(7 downto 0);
+  signal b_b   : std_logic_vector(7 downto 0);
+  signal valid : std_logic;
+  signal dout  : std_logic;
+  signal ready : std_logic;
+  signal res   : std_logic;
+begin
+  DUT: entity work.gc_argb_led_drv
+    generic map (
+      g_clk_freq => C_clk_freq
+    )
+    port map (
+      clk_i => clk,
+      rst_n_i => rst_n,
+      g_i => b_g,
+      r_i => b_r,
+      b_i => b_b,
+      valid_i => valid,
+      dout_o => dout,
+      ready_o => ready,
+      res_o => res
+    );
+
+  process
+  begin
+    clk <= not clk;
+    wait for (1_000_000_000 / C_CLK_FREQ / 2) * 1 ns;
+  end process;
+
+  process
+  begin
+    wait until rising_edge(clk);
+    rst_n <= '1';
+    wait;
+  end process;
+
+  process
+  begin
+    valid <= '0';
+    loop
+      wait until rising_edge(clk);
+      exit when ready = '1';
+    end loop;
+    b_g <= x"80";
+    b_r <= x"7f";
+    b_b <= x"c8";
+    valid <= '1';
+    wait until rising_edge(clk);
+    valid <= '0';
+    wait;
+  end process;
+end arch;
\ No newline at end of file