trigger pipeline

39df4b9e · Alén Arias Vázquez · 9f32926a · 39df4b9e
Commit 39df4b9e authored Mar 31, 2023 by Alén Arias Vázquez 😎
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spec_masterfip_mt.vhd top/spec/spec_masterfip_mt.vhd +0 -1

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--- a/top/spec/spec_masterfip_mt.vhd
+++ b/top/spec/spec_masterfip_mt.vhd
@@ -343,7 +343,6 @@ architecture rtl of spec_masterfip_mt is
  signal spec_led               : std_logic_vector(7 downto 0);
  signal fd_txd                 : std_logic;

-
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================