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MasterFIP - Gateware
Commit 68a9872f authored by Evangelia Gousiou's avatar Evangelia Gousiou
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Merge tag 'v1.0' 

version in CHARM

Conflicts:
	.gitmodules
	ip_cores/general-cores
	ip_cores/gn4124-core
	ip_cores/wr-cores
	rtl/fmc_masterFIP_core.vhd
	rtl/fmc_masterFIP_mezz.vhd
	rtl/fmc_masterfip_csr.vhd
	rtl/masterFIP_pkg.vhd
	rtl/masterfip_rx.vhd
	rtl/masterfip_tx.vhd
	rtl/wbgen/fmc_masterfip_csr.wb
	sim/spec/data_vectors/masterFIP_test.vec
	sim/spec/testbench/tb_masterFIP.vhd
	syn/spec/spec_masterfip_mt.xise
	top/spec/spec_masterFIP.ucf
	top/spec/spec_masterFIP.vhd
parents 9db4f36e 3591d52b
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.gitmodules
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[submodule "ip_cores/wr-node-core"]
path = ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "ip_cores/nanofip"]
path = ip_cores/nanofip
url = git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
[submodule "ip_cores/gn4124-core"]
path = ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "ip_cores/wr-cores"]
path = ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
\ No newline at end of file
doc/review_02032017/denia_comments.txt 0 → 100644
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masterFIP review comments:
General comments:
==================
- Very readable code, useful comments, and very useful diagrams at the top.
- Repo seems to be in good order.
- Most processes are missing the p_ prefix.
- Optionally, use the name of the process at the end, i.e.: end process p_process_name.
- Indentation at some places needs to be corrected.
fmc_massterFIP_core.vhd
========================
- Line 517, 534 and 549: Expression core_rst = '1' or rx_rst = '1' used in 3 places.
Use one signal assignement and use that instead for optimisation.
- Same for core_rst_n = '0' or fd_host_rst = '1' which is used in various places.
- Some indentation may be improved, eg in: cmp_masterfip_tx.
- fd_wdgn signal should be renamed fd_wdg_n, same for fd_rstn_o-> fd_rst_n_o
- I know chipscope is commented, but, the port map has the wrong syntax
(<= instead of => and the semicolons at the end)
masterfip_tx:
=============
- I found the suffixes to express 1-tick delays a little confusing. You
have in the same process:
line 304 last_data_byte_p_d <= last_data_byte_p_tmp;
last_data_byte_p <= last_data_byte_p_d;
And this:
line 307
byte_request_accept_p_d1 <= byte_request_accept_p_tmp;
byte_request_accept_p_d2 <= byte_request_accept_p_d1;
Why not use the same suffix scheme? preferably use "_dn" for both sets of expressions,
in agreement with VHDL guidelines table 3 p12. "_tmp" can be replaced by
"_d0"?
masterfip_rx:
=============
- s_ suffix for signals is optional. I think its use is especially
redundant since it is not used for all the signals in this module.
- Line 270: create_32bit_words process name should have the p_ prefix.
- Line 300: use p_ prefix for process name
- Line 263: bytes_c_rst expression:
bytes_c_rst <= '1' when (rst_i = '1' or rx_rst_i = '1') else '0';
effectively means that bytes_c_rst is the same value as (rst_i = '1' or rx_rst_i = '1').
Make it as an assignement (?)
bytes_c_rst <= rst_i or rx_rst_i;
- The expression (rst_i = '1' or rx_rst_i = '1') is evaluated at 4
separate occasions. Would it be better to assign it to a signal and
perform the OR only once? (ties in with previous remark).
- In process data_transfer_to_regs:
- add p_ prefix to process name.
- The operation: word32_num <= word32_num + 1;
seems to be performed no matter what the condition is (apart from reset condition)
could be performed once straight after the first else?
- In...
.....
if word32_num = 0 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
elsif (unsigned(rx_byte_index)-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
.....
It looks like the two conditions could be grouped under one condition
with an OR as the outcome is the same. In fact, it seems that most
outcomes are the same apart from Line 338. It seems the code could be
much more compact.
leds_manager.vhd
=================
Could this core be made more generic by removing all the TDC-specific
references in comments and port names and moved inside general core ?
- Line 96: add prefix g_ for generic values_for_simul
- In process pulse_generator, all acam_channel(2 downto 0) values other
than 0, 1, 2, 3 result in ch5 LED being lit. Is this okay functionally?
Wouldn it better to add the "="100" condition and send all the other
possibilities to the final else statement (all channels off?)
decr_counter.vhd
=================
- Use c_ prefix for constants.
- Couldn't signal one <= zeroes + "1" be made into a constant, something like:
constant c_one : unsigned (width-1 downto 0):= to_unsigned (1, width-1) (?)
- Is counter_is_zero_o supposed to be 1-tick long? if so add _p suffix,
else it could be assigned outside the process like this?
counter_is_zero_o <= '1' when counter = zeroes else "0";
- Also seems like since decrement operation is present in most
conditions, the code could be made more compact.
incr_counter.vhd
=================
- s_counter does not need prefix.
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# emacs org-mode options and definitions, just ignore
#+OPTIONS: toc:nil
#+OPTIONS: ^:nil
#+TITLE: Comments for masterFIP GW review <2017-03-16 Thu>
* Project/Synthesis/PAR
- [+] 3943 warnings during synthesis
- [+] ucf: "TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback" points to non-existing
node 'U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback'.
- [-] 120+ warnings about missing/duplicates files when we first open the .xise project file, and
the messages keep reappearing while we use the tool
- [-] Project hierarchy shows too many unused files (not under spec_masterfip_mt entity)
- [-] running hdlmake in syn/spec does not work
- [-] many (~50) synthesis-generated files not git-ignored
- [-] if not a build script for wbgen, at least a README with how you expect the wbgen2 command to
be invoked should be provided
* Simulation
- [!] Error: (vcom-19) Failed to access library 'nanofip_lib' at "nanofip_lib" (Modelsim SE-64
10.2a, Linux) This is due to case-sensitivity in Linux. Solution: replace "vlib nanoFIP_lib"
with "vlib nanofip_lib" or, alternatively, replace "vcom -work nanofip_lib" with "vcom -work
nanoFIP_lib"
- [!] Error: (vcom-7) Failed to open design unit file "../../sim/spec/testbench/nanofip_lib/*" in
read mode. Again, this is due to case-sensitivity in Linux, since the folder commited in git is
actually sim/spec/testbench/nanoFIP_lib
- [+] Trying to step into the code with Modelsim produces: Error opening
/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/unisims/primitive/PLL_ADV.vhd. This path does not exist in
my system.
- [+] Fix warnings "numeric_std.to_integer metavalue detected, returning 0" (alternatively, use
"set NumericStdNoWarnings 1" after the call to vsim in your do files, suboptimal solution because
it might also hide useful metavalue warnings)
- [-] After clearing the metavalue warnings, have a look also at the remaining warnings
- [-] Some signals are always 'X', if they are not useful in simulation, just remove them
- [-] group signal waveforms
- [-] split compilation (vcom) from running in separate "do" files, invoke them both from a top do
file (eg. compile.do + run.do => sim.do)
- [-] many (~100) simulation-generated files not git-ignored
- [?] Do you need the "vlog $env(XILINX)/verilog/src/glbl.v"? If not, remove it, otherwise users
might get the error "can't read "env(XILINX)": no such variable" if they haven't set this
environment variable.
* Design
- [?] rtl: is leds_manager.vhd used at all? what about carrier_info.vhd, free_counter.vhd, and
perhaps others? If not, it's better to delete them from the repository.
- [?] rtl: why is wf_package.vhd declared here AND in ip-cores/nanofip?
- [?] top: is synthesis_descriptor.vhd used?
- [*] the whole nanofip as ip-core of masterfip seems a bit counter-intuitive. If there are things
used by both, the should belong to a "fip" project, and both nano- and master- should use them.
** masterFIP_pkg
- [-] constants should have lower case "c" (I think)
** spec_masterfip_mt
*** fmc_masterFIP_core
- [-] it would be nice to have a bit more hierachy in this module, with less low-level processes
and modules lying around (eg. counter modules, assignments to wb registers) , to highlight the
high-level structure of the core.
- [?] why do you use two decreasing counter modules (wf_decr_counter and decr_counter)?
- [?] why is speed_X_i not a 2-bit vector?
- [?] would it be interesting for diagnostics to monitor if/when counters overflow?
- [?] why is reg_to_mt.fd_wdg_tstamp_i one bit larger than macrocyc_cnt?
- [*] cmp_ext_sync_deglitch_p_detect and cmp_fd_wdgn_deglitch_p_detect introduce one unnecessary
FF/latency cycle
- [*] we should introduce generic up/down counters to general-cores
**** masterfip_tx
- [-] synch_signals process could be replaced by 2x gc_sync_ffs
- [?] more importantly, why do you resync these two signals?
**** masterfip_rx
- [?] can't you use general-cores for cmp_rx_deglitcher? (perhaps think about it also in nanofip
project)
- [?] did you make up your mind about what to connect to nfip_rst_i port of cmp_rx_deglitcher? if
yes, remove the inline comment
* Legend
- [!] = fatal
- [+] = important
- [-] = minor
- [?] = question
- [*] = note
etherbone-core @ c1e676dc
Subproject commit c1e676dc9d35028910c50431d70328e522396c89
general-cores @ 1c2dd12b
Subproject commit 97bc71975252b32cf8a47ba895f7010734f015e5
Subproject commit 1c2dd12b1bceeab3b32b41c3522931c658ad15a7
gn4124-core @ e3a0bf97
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
nanofip @ 752512a8
Subproject commit 752512a82a05ce5ac4c69ad19f68921762bdd512
wr-cores @ d0d4d09d
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
Subproject commit d0d4d09d5f0355dfc6c078171bc6856e580a7496
wr-node-core @ 96a78592
Subproject commit 96a78592b4d20140bf13662476605ab7e96d7710
rtl/Manifest.py 0 → 100644
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files=[ "carrier_info.vhd",
"decr_counter.vhd",
"fmc_masterFIP_core.vhd",
"fmc_masterfip_csr.vhd",
"fmc_masterfip_eic.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"masterFIP_pkg.vhd",
"masterfip_rx.vhd",
"masterfip_tx.vhd",
"from_nanofip/wf_crc.vhd",
"from_nanofip/wf_decr_counter.vhd",
"from_nanofip/wf_incr_counter.vhd",
"from_nanofip/wf_package.vhd",
"from_nanofip/wf_rx_deglitcher.vhd",
"from_nanofip/wf_rx_deserializer.vhd",
"from_nanofip/wf_rx_osc.vhd",
"from_nanofip/wf_tx_osc.vhd",
"from_nanofip/wf_tx_serializer.vhd" ];
rtl/decr_counter.vhd
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--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -17,17 +17,7 @@
-- "Counter done" signal asserted simultaneous to "current count value = 0". |
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
......@@ -55,7 +45,6 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for decr_counter
--=================================================================================================
......@@ -66,17 +55,12 @@ entity decr_counter is
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signals from any unit
counter_load_i : in std_logic; -- loads counter with counter_top_i value
counter_load_i : in std_logic; -- loads counter with counter_top_i
counter_top_i : in std_logic_vector(width-1 downto 0); -- counter start value
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic); -- counter empty indication
......@@ -89,16 +73,15 @@ end decr_counter;
architecture rtl of decr_counter is
constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
constant zeroes : unsigned(width-1 downto 0) :=(others=>'0');
signal one : unsigned(width-1 downto 0);
signal counter : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
decr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
......
rtl/fmc_masterFIP_core.vhd
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rtl/incr_counter.vhd
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--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -12,15 +12,8 @@
---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -46,32 +39,22 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for incr_counter
--=================================================================================================
entity incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
generic(g_counter_lgth : natural := 32); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
clk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
clk_i : in std_logic; -- 40 MHz clock
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
counter_is_full_o : out std_logic); -- counter full indication, when all bits are '1'
end entity incr_counter;
......@@ -92,7 +75,6 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -107,7 +89,6 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(s_counter);
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
......
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#!/bin/bash
wbgen2 -V masterfip_wbgen2_csr.vhd -H record -p masterfip_wbgen2_pkg.vhd -s defines -C masterfip_wbgen2_csr.h -D masterfip_wbgen2_csr.html masterfip_csr.wb
echo ""
echo "Moving WB generated files to the following locations..."
echo ""
mv -v ./master_wbgen2_csr.vhd ../.
mv -v ./master_wbgen2_pkg.vhd ../.
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peripheral {
name = "masterFIP EIC";
description = "FMC masterfip embedded interrrupt controller.";
hdl_entity = "fmc_masterfip_eic";
prefix = "fmc_masterfip_eic";
irq {
name = "start new macrocycle";
description = "start new macrocycle either because there is a new sync pulse or because the counter expired (rising edge sensitive).";
prefix = "macrocy_start";
trigger = EDGE_RISING;
};
irq {
name = "silence time expired";
description = "silence time expired(rising edge sensitive).";
prefix = "silen_time_expire";
trigger = EDGE_RISING;
};
irq {
name = "turnaround time expired";
description = "turnaround time expired(rising edge sensitive).";
prefix = "turnar_time_expire";
trigger = EDGE_RISING;
};
irq {
name = "end of frame transmission";
description = "end of frame transmission(rising edge sensitive).";
prefix = "tx_completed";
trigger = EDGE_RISING;
};
irq {
name = "reception of a new fss";
description = "reception of a new fss(rising edge sensitive).";
prefix = "rx_fss_ok";
trigger = EDGE_RISING;
};
irq {
name = "reception of a new complete frame";
description = "reception of a new complete frame(rising edge sensitive).";
prefix = "rx_frame_ok";
trigger = EDGE_RISING;
};
irq {
name = "reception of a frame with wrong crc";
description = "reception of a frame with wrong crc(rising edge sensitive).";
prefix = "rx_crc_wrong";
trigger = EDGE_RISING;
};
};
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1 -- bit rate: 31.25 kbit/s(0), 1 Mbit/s(1), 2.5 Mbit/s(2)
10001110111001111 -- gx bit polynomial for CRC
101010101XX10XX0 -- FSS value
1XXXX101 -- FES value
03 -- id_dat frame control byte
02 -- rp_dat frame control byte
14 -- Presence Variable address
10 -- Identification Variable address
91 -- Broadcast Variable address
05 -- Consumed Variable address
06 -- Produced Variable address
E0 -- Reset Variable address
40 -- pdu_type byte
05 -- mps byte
2000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/board_settings_config.txt 0 → 100644
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vcc -- c_id_3 can take the values (gnd, vcc, sd0, sd1)
sd0 -- c_id_2 can take the values (gnd, vcc, sd0, sd1)
sd1 -- c_id_1 can take the values (gnd, vcc, sd0, sd1)
gnd -- c_id_0 can take the values (gnd, vcc, sd0, sd1)
gnd -- m_id_3 can take the values (gnd, vcc, sd0, sd1)
sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is validboard
\ No newline at end of file
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FALSE -- Truncate preamble
FALSE -- Insert violation error for one clk cycle
0 ps -- Jitter error inserted on the manchester encoded signal
0 -- Number of bits per byte truncated in reception (integer 1 to 8)
0 ps -- TXERR error length
0 ps -- WDGN error length
20000 ms --++ time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
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-------------------------------------------------------------------------------
-- masterFIP_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
......@@ -14,6 +14,7 @@ init
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
......@@ -29,122 +30,227 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
-- reset active
wr 0000000000030000 F CAFE0000
wait %d20
-- core and FD reset active
wr 000000000010000 F CAFE0003
wait %d40
-- FD reset active
wr 0000000000010000 F CAFE0002
wait %d40
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 0000000000030018 F 80007D00
wait %d20
--wr 000000000001001C F 80004880
--wait %d20
--wr 000000000001001C F 00002A6D
-- turnar counter top
wr 000000000003001C F 000007D0
wait %d20
--wr 0000000000010020 F 000007D0
--wait %d20
-- silen counter top
wr 0000000000030020 F 00000FA0
wait %d20
--wr 000000000010024 F 00000FA0
--wait %d20
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
-- tx_rst
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030158 F 00000305
wr 000000000001017C F 00000305
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 0000000000010040 F 00000202
wait %d20000
--------------- RP_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
-- tx_rst
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030154 F 00000002
wr 0000000000010178 F 00000002
wait %d20
-- data bytes
wr 0000000000030158 F BBAA0340
wr 000000000001017C F BBAA0340
wait %d20
wr 000000000003015c F EEDDCC05
wr 0000000000010180 F EEDDCC05
wait %d20
wr 0000000000030160 F 0A090807
-- tx_start
wr 0000000000010040 F 00000502
wait %d20000
wr 0000000000010040 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wait %d20
wr 0000000000030164 F 0E0D0C0B
-- control byte of id_dat
wr 0000000000010178 F 00000003
wait %d20
wr 0000000000030168 F 06060605
-- data bytes varid = 1403 for agent to send identification
wr 000000000001017C F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 0000000000030034 F 00000502
wr 0000000000010040 F 00000202
wait %d200
-- deactivate tx_start
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000010070 F 00000002
wait %d20
rd 0000000000010040 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000314
-- data bytes varid = 0603 for agent to produce
wr 000000000001017C F 00000306
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 0000000000010040 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000002
rd 0000000000010070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 000000000003004c F 00000050
rd 0000000000010058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 000000000001005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000010060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000001006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000001007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000001008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000010098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000001009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000100DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000030154 F 00000040
wr 0000000000010178 F 00000040
wait %d20
-- rx_rst
wr 0000000000030040 F 00000001
wr 0000000000010040 F 00000001
wait %d20
-- tx_start
wr 0000000000030034 F 00000002
wr 0000000000010040 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/data_vectors/user_logic_config.txt 0 → 100644
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25 ns -- User clock period (should not be modified during test)
25 ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
20000 ms -- validity time: time for which the configuration above is valid
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rtl/from_nanofip/wf_rx_deserializer.vhd → sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd
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......@@ -115,6 +115,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deserializer
--=================================================================================================
......
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action = "synthesis"
target="xilinx"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_masterfip_wrnode.xise"
top_module = "spec_top"
syn_tool = "ise"
modules = { "local" : [ "../../top/spec_wrnode" ] }
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top/spec/synthesis_descriptor.vhd
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