Merge branch '38-release-4-3-0' into 'master'

Resolve "release 4.3.0" Closes #38 See merge request be-cem-edl/common/mockturtle!29

Merge branch '38-release-4-3-0' into 'master'
Resolve "release 4.3.0" Closes #38 See merge request be-cem-edl/common/mockturtle!29
7ec23c8f · Dimitris Lampridis · 62dd78e4 · a9b8030d · 7ec23c8f · 7ec23c8f
Commit 7ec23c8f authored Nov 14, 2023 by Dimitris Lampridis
11 changed files
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -26,6 +26,18 @@ software_build:
  variables:
    EDL_CI_SW_PATHS: software

+sim_fw_build:
+  extends: .build_urv_fw
+  variables:
+    EXTRA2_CFLAGS: -DSIMULATION
+  script:
+    - make -C tests/firmware
+    - make -C demos firmware
+  artifacts:
+    paths:
+      - tests/firmware/**/*.bin
+      - demos/**/*.bin
+
 test_fw_build:
  extends: .build_urv_fw
  variables:

--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -9,6 +9,22 @@ Change Log
 Format: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
 Versioning: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_

+[4.3.0] - 2023-11-14
+====================
+Added
+-----
+- [bld] build distribution tarball with all binaries and development files (#36)
+
+Changed
+-------
+- [sw/fw] use GCC toolchain v11.2 for RISC-V firmware compilation (#37)
+- [bld] use common EDL CI pipelines (#35)
+
+Fixed
+-----
+- [sw/py] fix calls to trtl_close() in TrtlDevice object destructor
+- [sw] fix bug in sync_id when used by multiple sync users on same HMQ (#34)
+
 [4.2.0] - 2023-06-12
 ====================
 Added

--- a/demos/Makefile
+++ b/demos/Makefile
@@ -13,11 +13,12 @@ DIRS += fmc-spec-carrier/software
 TRTL ?= ..
 TRTL_SW = $(TRTL)/software

-all clean cleanall modules install modules_install: $(DIRS)
+all clean cleanall modules install modules_install firmware: $(DIRS)

 clean: TARGET = clean
 cleanall: TARGET = cleanall
 modules: TARGET = modules
+firmware: TARGET = firmware
 install: TARGET = install
 modules_install: TARGET = modules_install


--- a/hdl/testbench/.gitlab-ci.yml
+++ b/hdl/testbench/.gitlab-ci.yml
@@ -4,9 +4,9 @@

 hdl_simulation:
  interruptible: true
-  stage: build
+  stage: validate
  when: manual
-  needs: []
+  needs: [sim_fw_build]
  tags:
    - questasim
    - "10.5c"

--- a/hdl/testbench/hmq_async_recv/Manifest.py
+++ b/hdl/testbench/hmq_async_recv/Manifest.py
@@ -27,7 +27,8 @@ include_dirs = [
    fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
 ]

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/hmq-async-recv defconfig all"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/hmq-async-recv defconfig all"

 files = [
    "main.sv",

--- a/hdl/testbench/mock_turtle_core/Manifest.py
+++ b/hdl/testbench/mock_turtle_core/Manifest.py
@@ -25,7 +25,8 @@ include_dirs = [
    fetchto + "/general-cores/sim/",
 ]

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/sim-verif defconfig all"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/sim-verif defconfig all"

 files = [
    "main.sv",

--- a/hdl/testbench/mt_eth_ep/Manifest.py
+++ b/hdl/testbench/mt_eth_ep/Manifest.py
@@ -18,7 +18,8 @@ include_dirs = [
    fetchto + "/general-cores/sim/",
 ]

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/rmq-udp-send defconfig all"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/rmq-udp-send defconfig all"

 files = [
    "main.sv",

--- a/hdl/testbench/spec_mt_demo/Manifest.py
+++ b/hdl/testbench/spec_mt_demo/Manifest.py
@@ -27,7 +27,8 @@ include_dirs = [
    fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
 ]

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"

 files = [
    "main.sv",

--- a/hdl/testbench/svec_mt_demo/Manifest.py
+++ b/hdl/testbench/svec_mt_demo/Manifest.py
@@ -27,7 +27,8 @@ include_dirs = [
    fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
 ]

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"

 files = [
    "main.sv",

--- a/software/firmware/Makefile
+++ b/software/firmware/Makefile
@@ -81,6 +81,9 @@ CFLAGS += -I$(TRTL_FW)/framework
 CFLAGS += -I$(TRTL_SW)/include
 CFLAGS += -DGIT_VERSION=$(RT_GIT_VERSION)

+EXTRA2_CFLAGS += # To be set by user on make line
+EXTRA_CFLAGS  += $(EXTRA2_CFLAGS)
+
 # used for firmware by trtl-project-creator
 CFLAGS += $(EXTRA_CFLAGS)


--- a/software/lib/PyMockTurtle/PyMockTurtle/PyMockTurtle.py
+++ b/software/lib/PyMockTurtle/PyMockTurtle/PyMockTurtle.py
@@ -203,7 +203,8 @@ class TrtlDevice(object):

    def __del__(self):
        if self.libtrtl is not None:
-            self.libtrtl.close(self.tkn)
+            if hasattr(self, 'tkn'):
+                self.libtrtl.trtl_close(self.tkn)
            self.libtrtl.trtl_exit()

    def __str__(self):
@@ -218,6 +219,8 @@ class TrtlDevice(object):
        self.libtrtl.trtl_open_by_id.argtypes = [c_uint]
        self.libtrtl.trtl_open_by_id.restype = c_void_p
        self.libtrtl.trtl_open_by_id.errcheck = self.__errcheck_pointer
+        self.libtrtl.trtl_close.argtypes = [c_void_p]
+        self.libtrtl.trtl_close.restype = None
        # ERROR
        self.libtrtl.trtl_strerror.argtypes = [c_int]
        self.libtrtl.trtl_strerror.restype = c_char_p