nanoFIP Test Bench Structure
The testbench is based on 2 sets of files:
- VHDL files emulating the components interacting with nanoFIP (fieldrive, user logic, etc...)
- TEXT files configuring and scheduling each particular test.
The text files are organized in 3 suites:
- Phase 1: Validation of functionality in operational conditions according to specs (all checks have to be OK)
- Phase 2: Validation of functionality in error conditions according to specs (simulation messages need to be analyzed)
- Phase 3: Study of behavior in unspecified limit conditions (the acceptable behavior has been defined case by case)
Below: excel files describing the 3 suites (Test_plan), and detailed timing for each test (Timeline_references)
G.Penacoba, June 2011