nanoFIP resets
Introduction
In memory mode (SLONE = '0') in order to reset the whole of the nanoFIP chip, the user has to activate both the RSTIN and the RST_I signals:
- RSTIN resets all the logic in the user 40 MHz clock domain, whereas
- RST_I resets all the logic in the WISHBONE clock domain.
The Power On Reset, RSTPON resets both “worlds”.
In stand-alone mode (SLONE = '1'), RSTIN resets all the logic in use.
Power on reset
Since in no Actel ProAsic3 documentation we could find a warrantee that all the flip-flops of the chip start at “0” right after power-up, we concluded that a Power On Reset is essential for nanoFIP. After a short survey summarized in this document (pages 1-6 only) we decided to use an R-C circuit that acts asynchronously and is removed synchronously.
RC circuit recommended for the Power On Reset
The RSTPON resets both the user and the WISHBONE logic,
therefore the de-assertion synchronization is realised in both worlds.
Two flip-flops are used for the synchronization, with the second used to
remove any metastability that might be caused by the RSTPON being
removed asynchronously and too close to the rising clock edge.
Note:* The RSTPON does not activate nanoFIP's RSTON output
PowerOnReset_synchronizers.png !
Synchronization of the Power On Reset de-assertion edge for the uclk
and wclk worlds
nanoFIP internal reset
nanoFIP logic running with the uclk is reset by:
- The RSTPON: the reset lasts for as long as the RSTPON is asserted plus 2 uclk cycles.
- The RSTIN: nanoFIP checks if RSTIN has stayed asserted for at least 4 uclk cycles (*) and then asserts the nanoFIP internal reset for 4 uclk cycles. nanoFIP functinal specification requires that the RSTIN should stay activated for at least 8 uclk cycles, but internally it was decided to check for only 4.
- The reset variable (E0..h): nanoFIP is validating the consumed frame (in terms of Control, PDU_TYPE, Length and FCS bytes) and checks if the first byte contains the station’s address; if so, it asserts nanoFIP’s internal reset for 4 uclk cycles.
nanoFIP WISHBONE logic running with the wclk is reset by:
- The RSTPON: the reset lasts for as long as the RSTPON is asserted, plus 2 wclk cycles.
- The RST_I: following the WISHBONE rule 3.15 "all self-starting state machines and counters in WISHBONE interfaces MUST initialize themselves at the rising wclk edge following the assertion of RST_I. They MUST stay in the initialized state until the rising wclk edge that follows the negation of RST_I".
FielDrive reset
nanoFIP asserts the output FD_RST when:
- The RSTPON is asserted: the reset lasts for as long as the RSTPON is asserted plus 2 uclk cycles.
- The RSTIN is asserted: nanoFIP checks if RSTIN has stayed asserted for 4 uclk cycles and then asserts the FD_RST for 4 FD_TXCK cycles.
- A valid reset variable (E0..h) has been received with the first byte containing the station address: nanoFIP asserts FD_RST for 4 FD_TXCK cycles.
User reset
nanoFIP asserts the output RSTON only
- after the reception of a valid reset variable (E0..h) with the second byte containing the station address; the RSTON stays asserted for 8 uclk cycles.
_Back to the Hints n' Tips Guide_
E.Gousiou, March 2012