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spec-stress-test
Commit a9fa0f6f authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix issues with SDB and point to master DDR3

parent bcbef14c
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Showing with 5 additions and 6 deletions
hdl/spec/rtl/spec_top_stress_test.vhd
View file @ a9fa0f6f
......@@ -295,7 +295,7 @@ architecture rtl of spec_stress_test is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(9 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
......@@ -303,10 +303,7 @@ architecture rtl of spec_stress_test is
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_device(c_wb_serdes_csr_sdb, x"00001500"),
6 => f_sdb_embed_device(c_wb_serdes_eic_sdb, x"00001600"),
7 => f_sdb_embed_repo_url(c_repo_url_sdb),
8 => f_sdb_embed_synthesis(c_synthesis_sdb),
9 => f_sdb_embed_integration(c_integration_sdb)
6 => f_sdb_embed_device(c_wb_serdes_eic_sdb, x"00001600")
);
-- VIC default vector setting
......
hdl/spec/syn/Manifest.py
View file @ a9fa0f6f
target = "xilinx"
action = "synthesis"
top_module = "spec_stress_test"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
......@@ -18,7 +20,7 @@ modules = { "local" : [ "../rtl",
"../../ip_cores/ddr_sync_fifo" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::develop",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::master",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::proposed_master" ]}
fetchto = "../../ip_cores"
......
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